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Commit c4fd66d2 authored by Shefali Jain's avatar Shefali Jain
Browse files

clk: qcom: Update BCR address to spare register 



The USB phy BCR addresses have been updated as
per HW design, update the address and the bit
associated. Also add support for dcc clocks for
DCC client to put across clock vote.

Change-Id: Ia1cc615cfe8f1de12a537714463b728b3eaa08d2
Signed-off-by: default avatarShefali Jain <shefjain@codeaurora.org>
parent e1d7d8cb

drivers/clk/qcom/debugcc-qcs405.c

+3 −0
Original line number Diff line number Diff line
@@ -110,6 +110,7 @@ static const char *const debug_mux_parent_names[] = { 
	"gcc_usb_hs_inactivity_timers_clk",

	"gcc_usb_hs_phy_cfg_ahb_clk",

	"gcc_usb_hs_system_clk",

	"gcc_dcc_clk",

	"apcs_mux_clk",

};
@@ -278,6 +279,8 @@ static struct clk_debug_mux gcc_debug_mux = { 
		0x64, 0x1FF, 0, 0xF000, 12, 4, 0x74000, 0x74000, 0x74000 },

		{ "gcc_usb_hs_system_clk", 0x60, 4, GCC,

		0x60, 0x1FF, 0, 0xF000, 12, 4, 0x74000, 0x74000, 0x74000 },

		{ "gcc_dcc_clk", 0x1B9, 4, GCC,

		0x1B9, 0x1FF, 0, 0xF000, 12, 4, 0x74000, 0x74000, 0x74000 },

		{ "apcs_mux_clk", 0x16A, CPU_CC, 0x000, 0x3, 8, 0x0FF },

	),

	.hw.init = &(struct clk_init_data){

drivers/clk/qcom/gcc-qcs405.c

+16 −2
Original line number Diff line number Diff line
@@ -1471,6 +1471,19 @@ static struct clk_branch gcc_blsp1_ahb_clk = { 
	},

};



static struct clk_branch gcc_dcc_clk = {

	.halt_reg = 0x77004,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x77004,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_dcc_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_blsp1_qup0_i2c_apps_clk = {

	.halt_reg = 0x6028,

	.halt_check = BRANCH_HALT,
@@ -2819,15 +2832,16 @@ static struct clk_regmap *gcc_qcs405_clocks[] = { 
	[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,

	[GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,

	[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,

	[GCC_DCC_CLK] = &gcc_dcc_clk.clkr,

};



static const struct qcom_reset_map gcc_qcs405_resets[] = {

	[GCC_GENI_IR_BCR] = {0x0F000},

	[GCC_USB_HS_BCR] = {0x41000},

	[GCC_USB2_HS_PHY_ONLY_BCR] = {0x41034},

	[GCC_USB2_HS_PHY_ONLY_BCR] = {0x0000C, 0},

	[GCC_QUSB2_PHY_BCR] = {0x4103C},

	[GCC_USB_HS_PHY_CFG_AHB_BCR] = {0x41038},

	[GCC_USB2A_PHY_BCR] = {0x41028},

	[GCC_USB2A_PHY_BCR] = {0x0000C, 1},

	[GCC_USB3_PHY_BCR] = {0x39004},

	[GCC_USB_30_BCR] = {0x39000},

	[GCC_USB3PHY_PHY_BCR] = {0x39008},