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Commit c4d922b1 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'msm-next' of git://people.freedesktop.org/~robclark/linux into drm-next 

 1) add LVDS support for mdp4 (tested with auo B101XTN01.0 panel)
 2) add B101XTN01.0 panel
 3) bit of gpu refactoring to prepare for addition of addition gpu
generations beyond just a3xx

* 'msm-next' of git://people.freedesktop.org/~robclark/linux:
  drm/msm/adreno: push dump/show stuff to base class
  drm/msm/adreno: bit of init refactoring
  drm/msm/adreno: move decision about what gpu to to load
  drm/msm/adreno: split adreno device out into it's own file
  drm/panel/simple: add optronics B101XTN01.0 (v3)
  drm/msm/mdp4: add LVDS panel support
  drm/msm/mdp4: fix blend setup with multiple crtcs
  drm/msm: update generated headers
parents 91b06a8e 3bcefb04

Documentation/devicetree/bindings/panel/auo,b101xtn01.txt

0 → 100644
+7 −0
Original line number Diff line number Diff line 
AU Optronics Corporation 10.1" WXGA TFT LCD panel



Required properties:

- compatible: should be "auo,b101xtn01"



This binding is compatible with the simple-panel binding, which is specified

in simple-panel.txt in this directory.

drivers/gpu/drm/msm/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ config DRM_MSM 
	depends on DRM

	depends on ARCH_QCOM || (ARM && COMPILE_TEST)

	select DRM_KMS_HELPER

	select DRM_PANEL

	select SHMEM

	select TMPFS

	default y

drivers/gpu/drm/msm/Makefile

+4 −0
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ ifeq (, $(findstring -W,$(EXTRA_CFLAGS))) 
endif



msm-y := \

	adreno/adreno_device.o \

	adreno/adreno_gpu.o \

	adreno/a3xx_gpu.o \

	hdmi/hdmi.o \
@@ -18,6 +19,8 @@ msm-y := \ 
	mdp/mdp_kms.o \

	mdp/mdp4/mdp4_crtc.o \

	mdp/mdp4/mdp4_dtv_encoder.o \

	mdp/mdp4/mdp4_lcdc_encoder.o \

	mdp/mdp4/mdp4_lvds_connector.o \

	mdp/mdp4/mdp4_irq.o \

	mdp/mdp4/mdp4_kms.o \

	mdp/mdp4/mdp4_plane.o \
@@ -39,5 +42,6 @@ msm-y := \ 
	msm_ringbuffer.o



msm-$(CONFIG_DRM_MSM_FBDEV) += msm_fbdev.o

msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o



obj-$(CONFIG_DRM_MSM)	+= msm.o

drivers/gpu/drm/msm/adreno/a2xx.xml.h

+3 −3
Original line number Diff line number Diff line
@@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are: 
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   9859 bytes, from 2014-06-02 15:21:30)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14477 bytes, from 2014-05-16 11:51:57)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  58020 bytes, from 2014-06-25 12:57:16)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  26602 bytes, from 2014-06-25 12:57:16)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14960 bytes, from 2014-07-27 17:22:13)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  58020 bytes, from 2014-08-01 12:22:48)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  41068 bytes, from 2014-08-01 12:22:48)



Copyright (C) 2013-2014 by the following authors:

- Rob Clark <robdclark@gmail.com> (robclark)

drivers/gpu/drm/msm/adreno/a3xx.xml.h

+6 −6
Original line number Diff line number Diff line
@@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are: 
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   9859 bytes, from 2014-06-02 15:21:30)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14477 bytes, from 2014-05-16 11:51:57)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  58020 bytes, from 2014-06-25 12:57:16)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  26602 bytes, from 2014-06-25 12:57:16)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14960 bytes, from 2014-07-27 17:22:13)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  58020 bytes, from 2014-08-01 12:22:48)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  41068 bytes, from 2014-08-01 12:22:48)



Copyright (C) 2013-2014 by the following authors:

- Rob Clark <robdclark@gmail.com> (robclark)
@@ -654,7 +654,7 @@ static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val) 
#define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT		0

static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val)

{

	return ((((uint32_t)(val * 40.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK;

	return ((((uint32_t)(val * 28.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK;

}



#define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET			0x0000206d
@@ -662,7 +662,7 @@ static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val) 
#define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT			0

static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)

{

	return ((((uint32_t)(val * 44.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;

	return ((((uint32_t)(val * 28.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;

}



#define REG_A3XX_GRAS_SU_MODE_CONTROL				0x00002070
@@ -1696,7 +1696,7 @@ static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) 
{

	return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK;

}

#define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK		0x3f000000

#define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK		0x7f000000

#define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT		24

static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)

{