pinctrl: rockchip: handle first half of rk3188-bank0 correctly (c4a532de) · Commits · e / devices / android_kernel_oneplus_sm8150

The first half of pinbank 0 only has one muxing function (as gpios) and does not have a special mux-register. Therefore ensure that no other mux function can be selected and also do not write to a non-existent register. Signed-off-by:

Heiko Stuebner <heiko@sntech.de> Signed-off-by:

Linus Walleij <linus.walleij@linaro.org>

drivers/pinctrl/pinctrl-rockchip.c

+14 −0

Original line number	Diff line number	Diff line
		@@ -350,6 +350,20 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
		u8 bit;
		u32 data;

		/*
		* The first 16 pins of rk3188_bank0 are always gpios and do not have
		* a mux register at all.
		*/
		if (bank->bank_type == RK3188_BANK0 && pin < 16) {
		if (mux != RK_FUNC_GPIO) {
		dev_err(info->dev,
		"pin %d only supports a gpio mux\n", pin);
		return -ENOTSUPP;
		} else {
		return 0;
		}
		}

		dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
		bank->bank_num, pin, mux);