Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c4415084 authored by Dmitry Fink's avatar Dmitry Fink Committed by Greg Kroah-Hartman
Browse files

OMAP: UART: Keep the TX fifo full when possible



Current logic results in interrupt storm since the fifo
is constantly below the threshold level. Change the logic
to fill all the available spaces in the fifo as long as
we have data to minimize the possibilty of underflow and
elimiate excessive interrupts.

Signed-off-by: default avatarDmitry Fink <finik@ti.com>
Signed-off-by: default avatarAlexander Savchenko <oleksandr.savchenko@ti.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent f64ffda6
Loading
Loading
Loading
Loading
+2 −1
Original line number Diff line number Diff line
@@ -315,7 +315,8 @@ static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
		serial_omap_stop_tx(&up->port);
		return;
	}
	count = up->port.fifosize / 4;
	count = up->port.fifosize -
		(serial_in(up, UART_OMAP_TXFIFO_LVL) & 0xFF);
	do {
		serial_out(up, UART_TX, xmit->buf[xmit->tail]);
		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+1 −0
Original line number Diff line number Diff line
@@ -366,6 +366,7 @@
#define UART_OMAP_MDR1_FIR_MODE		0x05	/* FIR mode */
#define UART_OMAP_MDR1_CIR_MODE		0x06	/* CIR mode */
#define UART_OMAP_MDR1_DISABLE		0x07	/* Disable (default state) */
#define UART_OMAP_TXFIFO_LVL		0x1A	/* TX FIFO fullness */

/*
 * These are definitions for the Exar XR17V35X and XR17(C|D)15X