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Commit c433eb70 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pinctrl-v4.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control fixes from Linus Walleij:
 "Three small pin control fixes for the v4.10 series. Very little to say
  about them, just driver fixes.

   - one fix to the AMD pinctrl ACPI glue

   - fix requests on the Meson driver

   - fix bitfield widths on Samsungs Exynos 5433"

* tag 'pinctrl-v4.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: samsung: Fix the width of PINCFG_TYPE_DRV bitfields for Exynos5433
  pinctrl: meson: fix gpio request disabling other modes
  pinctrl/amd: Set the level based on ACPI tables
parents b4007927 1259fedd

drivers/pinctrl/meson/pinctrl-meson.c

+1 −1
Original line number Diff line number Diff line
@@ -212,7 +212,7 @@ static int meson_pmx_request_gpio(struct pinctrl_dev *pcdev, 
{

	struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);



	meson_pmx_disable_other_groups(pc, range->pin_base + offset, -1);

	meson_pmx_disable_other_groups(pc, offset, -1);



	return 0;

}

drivers/pinctrl/pinctrl-amd.c

+7 −12
Original line number Diff line number Diff line
@@ -382,26 +382,21 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 
{

	int ret = 0;

	u32 pin_reg;

	unsigned long flags;

	bool level_trig;

	u32 active_level;

	unsigned long flags, irq_flags;

	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);

	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);



	spin_lock_irqsave(&gpio_dev->lock, flags);

	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);



	/*

	 * When level_trig is set EDGE and active_level is set HIGH in BIOS

	 * default settings, ignore incoming settings from client and use

	 * BIOS settings to configure GPIO register.

	/* Ignore the settings coming from the client and

	 * read the values from the ACPI tables

	 * while setting the trigger type

	 */

	level_trig = !(pin_reg & (LEVEL_TRIGGER << LEVEL_TRIG_OFF));

	active_level = pin_reg & (ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);



	if(level_trig &&

	   ((active_level >> ACTIVE_LEVEL_OFF) == ACTIVE_HIGH))

		type = IRQ_TYPE_EDGE_FALLING;

	irq_flags = irq_get_trigger_type(d->irq);

	if (irq_flags != IRQ_TYPE_NONE)

		type = irq_flags;



	switch (type & IRQ_TYPE_SENSE_MASK) {

	case IRQ_TYPE_EDGE_RISING:

drivers/pinctrl/samsung/pinctrl-exynos.c

+51 −40
Original line number Diff line number Diff line
@@ -56,6 +56,17 @@ static const struct samsung_pin_bank_type bank_type_alive = { 
	.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },

};



/* Exynos5433 has the 4bit widths for PINCFG_TYPE_DRV bitfields. */

static const struct samsung_pin_bank_type exynos5433_bank_type_off = {

	.fld_width = { 4, 1, 2, 4, 2, 2, },

	.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },

};



static const struct samsung_pin_bank_type exynos5433_bank_type_alive = {

	.fld_width = { 4, 1, 2, 4, },

	.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },

};



static void exynos_irq_mask(struct irq_data *irqd)

{

	struct irq_chip *chip = irq_data_get_irq_chip(irqd);
@@ -1335,82 +1346,82 @@ const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = { 


/* pin banks of exynos5433 pin-controller - ALIVE */

static const struct samsung_pin_bank_data exynos5433_pin_banks0[] = {

	EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),

	EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),

	EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),

	EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),

	EXYNOS_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1),

	EXYNOS_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1),

	EXYNOS_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1),

	EXYNOS_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1),

	EXYNOS_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1),

	EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),

	EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),

	EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),

	EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),

	EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1),

	EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1),

	EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1),

	EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1),

	EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1),

};



/* pin banks of exynos5433 pin-controller - AUD */

static const struct samsung_pin_bank_data exynos5433_pin_banks1[] = {

	EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),

	EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),

	EXYNOS5433_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),

	EXYNOS5433_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),

};



/* pin banks of exynos5433 pin-controller - CPIF */

static const struct samsung_pin_bank_data exynos5433_pin_banks2[] = {

	EXYNOS_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00),

	EXYNOS5433_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00),

};



/* pin banks of exynos5433 pin-controller - eSE */

static const struct samsung_pin_bank_data exynos5433_pin_banks3[] = {

	EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00),

	EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00),

};



/* pin banks of exynos5433 pin-controller - FINGER */

static const struct samsung_pin_bank_data exynos5433_pin_banks4[] = {

	EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00),

	EXYNOS5433_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00),

};



/* pin banks of exynos5433 pin-controller - FSYS */

static const struct samsung_pin_bank_data exynos5433_pin_banks5[] = {

	EXYNOS_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00),

	EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04),

	EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08),

	EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c),

	EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10),

	EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14),

	EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00),

	EXYNOS5433_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04),

	EXYNOS5433_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08),

	EXYNOS5433_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c),

	EXYNOS5433_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10),

	EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14),

};



/* pin banks of exynos5433 pin-controller - IMEM */

static const struct samsung_pin_bank_data exynos5433_pin_banks6[] = {

	EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00),

	EXYNOS5433_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00),

};



/* pin banks of exynos5433 pin-controller - NFC */

static const struct samsung_pin_bank_data exynos5433_pin_banks7[] = {

	EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),

	EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),

};



/* pin banks of exynos5433 pin-controller - PERIC */

static const struct samsung_pin_bank_data exynos5433_pin_banks8[] = {

	EXYNOS_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00),

	EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04),

	EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08),

	EXYNOS_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c),

	EXYNOS_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10),

	EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14),

	EXYNOS_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18),

	EXYNOS_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c),

	EXYNOS_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20),

	EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24),

	EXYNOS_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28),

	EXYNOS_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c),

	EXYNOS_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30),

	EXYNOS_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34),

	EXYNOS_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38),

	EXYNOS_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c),

	EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),

	EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00),

	EXYNOS5433_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04),

	EXYNOS5433_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08),

	EXYNOS5433_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c),

	EXYNOS5433_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10),

	EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14),

	EXYNOS5433_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18),

	EXYNOS5433_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c),

	EXYNOS5433_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20),

	EXYNOS5433_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24),

	EXYNOS5433_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28),

	EXYNOS5433_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c),

	EXYNOS5433_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30),

	EXYNOS5433_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34),

	EXYNOS5433_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38),

	EXYNOS5433_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c),

	EXYNOS5433_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),

};



/* pin banks of exynos5433 pin-controller - TOUCH */

static const struct samsung_pin_bank_data exynos5433_pin_banks9[] = {

	EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),

	EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),

};



/*

drivers/pinctrl/samsung/pinctrl-exynos.h

+31 −0
Original line number Diff line number Diff line
@@ -90,6 +90,37 @@ 
		.pctl_res_idx   = pctl_idx,             \

	}						\



#define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs)		\

	{							\

		.type		= &exynos5433_bank_type_off,	\

		.pctl_offset	= reg,				\

		.nr_pins	= pins,				\

		.eint_type	= EINT_TYPE_GPIO,		\

		.eint_offset	= offs,				\

		.name		= id				\

	}



#define EXYNOS5433_PIN_BANK_EINTW(pins, reg, id, offs)		\

	{							\

		.type		= &exynos5433_bank_type_alive,	\

		.pctl_offset	= reg,				\

		.nr_pins	= pins,				\

		.eint_type	= EINT_TYPE_WKUP,		\

		.eint_offset	= offs,				\

		.name		= id				\

	}



#define EXYNOS5433_PIN_BANK_EINTW_EXT(pins, reg, id, offs, pctl_idx) \

	{							\

		.type           = &exynos5433_bank_type_alive,	\

		.pctl_offset    = reg,				\

		.nr_pins        = pins,				\

		.eint_type      = EINT_TYPE_WKUP,		\

		.eint_offset    = offs,				\

		.name           = id,				\

		.pctl_res_idx   = pctl_idx,			\

	}							\



/**

 * struct exynos_weint_data: irq specific data for all the wakeup interrupts

 * generated by the external wakeup interrupt controller.