Loading Documentation/devicetree/bindings/display/msm/sde.txt +1 −0 Original line number Diff line number Diff line Loading @@ -208,6 +208,7 @@ Optional properties: - qcom,sde-te-size: A u32 value indicates the te block address range. - qcom,sde-te2-size: A u32 value indicates the te2 block address range. - qcom,sde-dsc-off: A u32 offset indicates the dsc block offset on pingpong. - qcom,sde-qdss-off: A u32 offset indicates the qdss block offset. - qcom,sde-dither-off: A u32 offset indicates the dither block offset on pingpong. - qcom,sde-dither-version: A u32 value indicates the dither block version. - qcom,sde-dither-size: A u32 value indicates the dither block address range. Loading arch/arm64/boot/dts/qcom/sm6150.dtsi +6 −1 Original line number Diff line number Diff line Loading @@ -640,7 +640,7 @@ }; cont_splash_memory: cont_splash_region@9c000000 { reg = <0x0 0x9c000000 0x0 0x02300000>; reg = <0x0 0x9c000000 0x0 0x01000000>; label = "cont_splash_region"; }; Loading @@ -649,6 +649,11 @@ label = "dfps_data_region"; }; disp_rdump_memory: disp_rdump_region@9c000000 { reg = <0x0 0x9c000000 0x0 0x01000000>; label = "disp_rdump_region"; }; dump_mem: mem_dump_region { compatible = "shared-dma-pool"; reusable; Loading arch/arm64/boot/dts/qcom/trinket-qrd.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -306,6 +306,7 @@ qcom,bl-pmic-pwm-period-usecs = <100>; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-dsi-bl-default-level = <102>; qcom,platform-te-gpio = <&tlmm 89 0>; qcom,platform-reset-gpio = <&tlmm 90 0>; }; Loading @@ -317,6 +318,7 @@ qcom,bl-pmic-pwm-period-usecs = <100>; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-dsi-bl-default-level = <102>; qcom,platform-reset-gpio = <&tlmm 90 0>; }; Loading drivers/gpu/drm/msm/dp/dp_display.c +32 −2 Original line number Diff line number Diff line Loading @@ -105,6 +105,8 @@ struct dp_display_private { struct work_struct connect_work; struct work_struct attention_work; struct mutex session_lock; bool suspended; bool hdcp_delayed_off; u32 active_stream_cnt; struct dp_mst mst; Loading Loading @@ -315,6 +317,19 @@ static void dp_display_hdcp_cb_work(struct work_struct *work) if (!dp->power_on || !dp->is_connected || atomic_read(&dp->aborted)) return; if (dp->suspended) { pr_debug("System suspending. Delay HDCP operations\n"); queue_delayed_work(dp->wq, &dp->hdcp_cb_work, HZ); return; } if (dp->hdcp_delayed_off) { if (dp->hdcp.ops && dp->hdcp.ops->off) dp->hdcp.ops->off(dp->hdcp.data); dp_display_update_hdcp_status(dp, true); dp->hdcp_delayed_off = false; } drm_dp_dpcd_readb(dp->aux->drm_aux, DP_SINK_STATUS, &sink_status); sink_status &= (DP_RECEIVE_PORT_0_STATUS | DP_RECEIVE_PORT_1_STATUS); if (sink_status < 1) { Loading Loading @@ -936,9 +951,7 @@ static void dp_display_clean(struct dp_display_private *dp) dp->power_on = false; mutex_lock(&dp->session_lock); dp->ctrl->off(dp->ctrl); mutex_unlock(&dp->session_lock); } static int dp_display_handle_disconnect(struct dp_display_private *dp) Loading Loading @@ -1694,6 +1707,13 @@ static int dp_display_pre_disable(struct dp_display *dp_display, void *panel) if (dp_display_is_hdcp_enabled(dp) && status->hdcp_state != HDCP_STATE_INACTIVE) { if (dp->suspended) { pr_debug("Can't perform HDCP cleanup while suspended. Defer\n"); dp->hdcp_delayed_off = true; goto stream; } flush_delayed_work(&dp->hdcp_cb_work); if (dp->mst.mst_active) { dp_display_hdcp_deregister_stream(dp, Loading Loading @@ -2627,14 +2647,24 @@ static int dp_display_remove(struct platform_device *pdev) static int dp_pm_prepare(struct device *dev) { struct dp_display_private *dp = container_of(g_dp_display, struct dp_display_private, dp_display); dp_display_set_mst_state(g_dp_display, PM_SUSPEND); dp->suspended = true; return 0; } static void dp_pm_complete(struct device *dev) { struct dp_display_private *dp = container_of(g_dp_display, struct dp_display_private, dp_display); dp_display_set_mst_state(g_dp_display, PM_DEFAULT); dp->suspended = false; } static const struct dev_pm_ops dp_pm_ops = { Loading drivers/gpu/drm/msm/dp/dp_hdcp2p2.c +12 −13 Original line number Diff line number Diff line Loading @@ -277,19 +277,22 @@ static void dp_hdcp2p2_reset(struct dp_hdcp2p2_ctrl *ctrl) static int dp_hdcp2p2_register(void *input, bool mst_enabled) { int rc; enum sde_hdcp_2x_device_type device_type; struct dp_hdcp2p2_ctrl *ctrl = (struct dp_hdcp2p2_ctrl *)input; struct dp_hdcp2p2_ctrl *ctrl = input; struct sde_hdcp_2x_wakeup_data cdata = {HDCP_2X_CMD_ENABLE}; rc = dp_hdcp2p2_valid_handle(ctrl); if (rc) return rc; if (mst_enabled) device_type = HDCP_TXMTR_DP_MST; cdata.device_type = HDCP_TXMTR_DP_MST; else device_type = HDCP_TXMTR_DP; cdata.device_type = HDCP_TXMTR_DP; cdata.context = ctrl->lib_ctx; rc = ctrl->lib->wakeup(&cdata); return sde_hdcp_2x_enable(ctrl->lib_ctx, device_type); return rc; } static int dp_hdcp2p2_on(void *input) Loading @@ -315,25 +318,21 @@ static void dp_hdcp2p2_off(void *input) { int rc; struct dp_hdcp2p2_ctrl *ctrl = (struct dp_hdcp2p2_ctrl *)input; struct sde_hdcp_2x_wakeup_data cdata = {HDCP_2X_CMD_INVALID}; struct sde_hdcp_2x_wakeup_data cdata = {HDCP_2X_CMD_DISABLE}; rc = dp_hdcp2p2_valid_handle(ctrl); if (rc) return; if (atomic_read(&ctrl->auth_state) != HDCP_STATE_AUTH_FAIL) { cdata.cmd = HDCP_2X_CMD_STOP; cdata.context = ctrl->lib_ctx; dp_hdcp2p2_wakeup_lib(ctrl, &cdata); } dp_hdcp2p2_set_interrupts(ctrl, false); dp_hdcp2p2_reset(ctrl); kthread_flush_worker(&ctrl->worker); sde_hdcp_2x_disable(ctrl->lib_ctx); cdata.context = ctrl->lib_ctx; ctrl->lib->wakeup(&cdata); } static int dp_hdcp2p2_authenticate(void *input) Loading Loading
Documentation/devicetree/bindings/display/msm/sde.txt +1 −0 Original line number Diff line number Diff line Loading @@ -208,6 +208,7 @@ Optional properties: - qcom,sde-te-size: A u32 value indicates the te block address range. - qcom,sde-te2-size: A u32 value indicates the te2 block address range. - qcom,sde-dsc-off: A u32 offset indicates the dsc block offset on pingpong. - qcom,sde-qdss-off: A u32 offset indicates the qdss block offset. - qcom,sde-dither-off: A u32 offset indicates the dither block offset on pingpong. - qcom,sde-dither-version: A u32 value indicates the dither block version. - qcom,sde-dither-size: A u32 value indicates the dither block address range. Loading
arch/arm64/boot/dts/qcom/sm6150.dtsi +6 −1 Original line number Diff line number Diff line Loading @@ -640,7 +640,7 @@ }; cont_splash_memory: cont_splash_region@9c000000 { reg = <0x0 0x9c000000 0x0 0x02300000>; reg = <0x0 0x9c000000 0x0 0x01000000>; label = "cont_splash_region"; }; Loading @@ -649,6 +649,11 @@ label = "dfps_data_region"; }; disp_rdump_memory: disp_rdump_region@9c000000 { reg = <0x0 0x9c000000 0x0 0x01000000>; label = "disp_rdump_region"; }; dump_mem: mem_dump_region { compatible = "shared-dma-pool"; reusable; Loading
arch/arm64/boot/dts/qcom/trinket-qrd.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -306,6 +306,7 @@ qcom,bl-pmic-pwm-period-usecs = <100>; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-dsi-bl-default-level = <102>; qcom,platform-te-gpio = <&tlmm 89 0>; qcom,platform-reset-gpio = <&tlmm 90 0>; }; Loading @@ -317,6 +318,7 @@ qcom,bl-pmic-pwm-period-usecs = <100>; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-dsi-bl-default-level = <102>; qcom,platform-reset-gpio = <&tlmm 90 0>; }; Loading
drivers/gpu/drm/msm/dp/dp_display.c +32 −2 Original line number Diff line number Diff line Loading @@ -105,6 +105,8 @@ struct dp_display_private { struct work_struct connect_work; struct work_struct attention_work; struct mutex session_lock; bool suspended; bool hdcp_delayed_off; u32 active_stream_cnt; struct dp_mst mst; Loading Loading @@ -315,6 +317,19 @@ static void dp_display_hdcp_cb_work(struct work_struct *work) if (!dp->power_on || !dp->is_connected || atomic_read(&dp->aborted)) return; if (dp->suspended) { pr_debug("System suspending. Delay HDCP operations\n"); queue_delayed_work(dp->wq, &dp->hdcp_cb_work, HZ); return; } if (dp->hdcp_delayed_off) { if (dp->hdcp.ops && dp->hdcp.ops->off) dp->hdcp.ops->off(dp->hdcp.data); dp_display_update_hdcp_status(dp, true); dp->hdcp_delayed_off = false; } drm_dp_dpcd_readb(dp->aux->drm_aux, DP_SINK_STATUS, &sink_status); sink_status &= (DP_RECEIVE_PORT_0_STATUS | DP_RECEIVE_PORT_1_STATUS); if (sink_status < 1) { Loading Loading @@ -936,9 +951,7 @@ static void dp_display_clean(struct dp_display_private *dp) dp->power_on = false; mutex_lock(&dp->session_lock); dp->ctrl->off(dp->ctrl); mutex_unlock(&dp->session_lock); } static int dp_display_handle_disconnect(struct dp_display_private *dp) Loading Loading @@ -1694,6 +1707,13 @@ static int dp_display_pre_disable(struct dp_display *dp_display, void *panel) if (dp_display_is_hdcp_enabled(dp) && status->hdcp_state != HDCP_STATE_INACTIVE) { if (dp->suspended) { pr_debug("Can't perform HDCP cleanup while suspended. Defer\n"); dp->hdcp_delayed_off = true; goto stream; } flush_delayed_work(&dp->hdcp_cb_work); if (dp->mst.mst_active) { dp_display_hdcp_deregister_stream(dp, Loading Loading @@ -2627,14 +2647,24 @@ static int dp_display_remove(struct platform_device *pdev) static int dp_pm_prepare(struct device *dev) { struct dp_display_private *dp = container_of(g_dp_display, struct dp_display_private, dp_display); dp_display_set_mst_state(g_dp_display, PM_SUSPEND); dp->suspended = true; return 0; } static void dp_pm_complete(struct device *dev) { struct dp_display_private *dp = container_of(g_dp_display, struct dp_display_private, dp_display); dp_display_set_mst_state(g_dp_display, PM_DEFAULT); dp->suspended = false; } static const struct dev_pm_ops dp_pm_ops = { Loading
drivers/gpu/drm/msm/dp/dp_hdcp2p2.c +12 −13 Original line number Diff line number Diff line Loading @@ -277,19 +277,22 @@ static void dp_hdcp2p2_reset(struct dp_hdcp2p2_ctrl *ctrl) static int dp_hdcp2p2_register(void *input, bool mst_enabled) { int rc; enum sde_hdcp_2x_device_type device_type; struct dp_hdcp2p2_ctrl *ctrl = (struct dp_hdcp2p2_ctrl *)input; struct dp_hdcp2p2_ctrl *ctrl = input; struct sde_hdcp_2x_wakeup_data cdata = {HDCP_2X_CMD_ENABLE}; rc = dp_hdcp2p2_valid_handle(ctrl); if (rc) return rc; if (mst_enabled) device_type = HDCP_TXMTR_DP_MST; cdata.device_type = HDCP_TXMTR_DP_MST; else device_type = HDCP_TXMTR_DP; cdata.device_type = HDCP_TXMTR_DP; cdata.context = ctrl->lib_ctx; rc = ctrl->lib->wakeup(&cdata); return sde_hdcp_2x_enable(ctrl->lib_ctx, device_type); return rc; } static int dp_hdcp2p2_on(void *input) Loading @@ -315,25 +318,21 @@ static void dp_hdcp2p2_off(void *input) { int rc; struct dp_hdcp2p2_ctrl *ctrl = (struct dp_hdcp2p2_ctrl *)input; struct sde_hdcp_2x_wakeup_data cdata = {HDCP_2X_CMD_INVALID}; struct sde_hdcp_2x_wakeup_data cdata = {HDCP_2X_CMD_DISABLE}; rc = dp_hdcp2p2_valid_handle(ctrl); if (rc) return; if (atomic_read(&ctrl->auth_state) != HDCP_STATE_AUTH_FAIL) { cdata.cmd = HDCP_2X_CMD_STOP; cdata.context = ctrl->lib_ctx; dp_hdcp2p2_wakeup_lib(ctrl, &cdata); } dp_hdcp2p2_set_interrupts(ctrl, false); dp_hdcp2p2_reset(ctrl); kthread_flush_worker(&ctrl->worker); sde_hdcp_2x_disable(ctrl->lib_ctx); cdata.context = ctrl->lib_ctx; ctrl->lib->wakeup(&cdata); } static int dp_hdcp2p2_authenticate(void *input) Loading