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Commit c35eaf7d authored by Sagar Dharia's avatar Sagar Dharia Committed by Karthikeyan Ramasubramanian
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tty: serial: Add UART driver snapshot for QUPv3 based core 



This snapshot is taken as of msm-4.9 'commit <e8a6a75991d4>
("Merge "usb: core: Add usb_set_interface_timeout API"")'.

UART driver for QUPv3 supports high-speed UART, and console UART
functionality, and supports FIFO and CPU_DMA mode.

CRs-Fixed: 2124301
Change-Id: Ia4bf290e1d3fe1982f266729ee3bf2a12bd93c12
Signed-off-by: default avatarGirish Mahadevan <girishm@codeaurora.org>
Signed-off-by: default avatarsagar Dharia <sdharia@codeaurora.org>
parent 0bd15f8d

Documentation/devicetree/bindings/serial/qcom,msm-geni-uart.txt

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* MSM Serial UART for GENI based cores.



The MSM serial UART driver supports low speed and high speed use-cases.

This is meant only for QUPv3 GENI based cores and isn't backwards compatible.

There is support for console usecases and for higher speed usecases that need

DMA.



Required properties:

- compatible: should contain "qcom,msm-geni-uart, qcom,msm-geni-console"

  for UART console usecases, "qcom,msm-geni-uart, qcom,msm-geni-serial-hs"

  for High Speed (HS) usecases.

- reg: Should contain UART register location and length.

- interrupts: Should contain UART core interrupts.

- clocks: clocks needed for UART, includes the core and AHB clock.

- pinctrl-names/pinctrl-0/1: The GPIOs assigned to this core. The names

  Should be "active" and "sleep" for the pin confuguration when core is active

  or when entering sleep state.

- qcom,wrapper-core: Wrapper QUPv3 core containing this UART controller.



Optional properties:

- qcom,wakeup-byte: Byte to be injected in the tty layer during wakeup isr.



Example:

qupv3_uart11: qcom,qup_uart@0xa88000 {

	compatible = "qcom,msm-geni-uart";

	reg = <0xa88000 0x7000>;

	reg-names = "se_phys";

	clock-names = "se-clk", "m-ahb", "s-ahb";

	clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,

		<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

		<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

	pinctrl-names = "default", "sleep";

	pinctrl-0 = <&qup_1_uart_3_active>;

	pinctrl-1 = <&qup_1_uart_3_sleep>;

	interrupts = <0 355 0>;

	qcom,wrapper-core = <&qupv3_0>;

	qcom,wakeup-byte = <0xFF>;

};

drivers/tty/serial/Kconfig

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@@ -1098,6 +1098,21 @@ config SERIAL_MSM_CONSOLE 
	select SERIAL_CORE_CONSOLE

	select SERIAL_EARLYCON



config SERIAL_MSM_GENI

	tristate "MSM on-chip GENI HW based serial port support"

	depends on ARCH_QCOM

	select SERIAL_CORE

	help

	    Serial driver for Qualcomm Technologies Inc's GENI based QUPv3

	    hardware.

	    The driver supports console and High speed UART functions.



config SERIAL_MSM_GENI_CONSOLE

	tristate "MSM on-chip GENI HW based console support"

	depends on SERIAL_MSM_GENI=y

	select SERIAL_CORE_CONSOLE

	select SERIAL_EARLYCON



config SERIAL_VT8500

	bool "VIA VT8500 on-chip serial port support"

	depends on ARCH_VT8500

drivers/tty/serial/Makefile

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@@ -63,6 +63,7 @@ obj-$(CONFIG_SERIAL_SGI_IOC3) += ioc3_serial.o 
obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o

obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o

obj-$(CONFIG_SERIAL_MSM) += msm_serial.o

obj-$(CONFIG_SERIAL_MSM_GENI) += msm_geni_serial.o

obj-$(CONFIG_SERIAL_NETX) += netx-serial.o

obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o

obj-$(CONFIG_SERIAL_OMAP) += omap-serial.o

drivers/tty/serial/msm_geni_serial.c

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+2483 −0

File added.

Preview size limit exceeded, changes collapsed.

include/uapi/asm-generic/ioctls.h

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@@ -80,6 +80,9 @@ 
#define TIOCGPTLCK	_IOR('T', 0x39, int) /* Get Pty lock state */

#define TIOCGEXCL	_IOR('T', 0x40, int) /* Get exclusive mode state */

#define TIOCGPTPEER	_IO('T', 0x41) /* Safely open the slave */

#define TIOCPMGET	0x544D	/* PM get */

#define TIOCPMPUT	0x544E	/* PM put */

#define TIOCPMACT	0x544F	/* PM is active */



#define FIONCLEX	0x5450

#define FIOCLEX		0x5451