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Commit c26adfe8 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "drm/msm/dsi-staging: modify htotal value for dfps calculation"

parents 4efb81a0 40c32691

drivers/gpu/drm/msm/dsi-staging/dsi_display.c

+5 −5
Original line number Diff line number Diff line
@@ -3875,7 +3875,7 @@ static int dsi_display_get_dfps_timing(struct dsi_display *display, 
		rc = dsi_display_dfps_calc_front_porch(

				curr_refresh_rate,

				timing->refresh_rate,

				DSI_H_TOTAL(timing),

				DSI_H_TOTAL_DSC(timing),

				DSI_V_TOTAL(timing),

				timing->v_front_porch,

				&adj_mode->timing.v_front_porch);
@@ -3886,7 +3886,7 @@ static int dsi_display_get_dfps_timing(struct dsi_display *display, 
				curr_refresh_rate,

				timing->refresh_rate,

				DSI_V_TOTAL(timing),

				DSI_H_TOTAL(timing),

				DSI_H_TOTAL_DSC(timing),

				timing->h_front_porch,

				&adj_mode->timing.h_front_porch);

		if (!rc)
@@ -5479,7 +5479,7 @@ int dsi_display_get_modes(struct dsi_display *display, 
					sub_mode, curr_refresh_rate);



				sub_mode->pixel_clk_khz =

					(DSI_H_TOTAL(&sub_mode->timing) *

					(DSI_H_TOTAL_DSC(&sub_mode->timing) *

					DSI_V_TOTAL(&sub_mode->timing) *

					sub_mode->timing.refresh_rate) / 1000;

			}
@@ -5664,8 +5664,8 @@ int dsi_display_validate_mode_vrr(struct dsi_display *display, 
			break;



		case DSI_DFPS_IMMEDIATE_HFP:

			if (abs(DSI_H_TOTAL(&cur_mode.timing) -

				DSI_H_TOTAL(&adj_mode.timing)) > 5)

			if (abs(DSI_H_TOTAL_DSC(&cur_mode.timing) -

				DSI_H_TOTAL_DSC(&adj_mode.timing)) > 5)

				pr_err("Mismatch hfp fps:%d new:%d given:%d\n",

				adj_mode.timing.refresh_rate,

				cur_mode.timing.h_front_porch,

drivers/gpu/drm/msm/dsi-staging/dsi_drm.c

+10 −0
Original line number Diff line number Diff line
@@ -65,6 +65,11 @@ static void convert_to_dsi_mode(const struct drm_display_mode *drm_mode, 
	dsi_mode->priv_info =

		(struct dsi_display_mode_priv_info *)drm_mode->private;



	if (dsi_mode->priv_info) {

		dsi_mode->timing.dsc_enabled = dsi_mode->priv_info->dsc_enabled;

		dsi_mode->timing.dsc = &dsi_mode->priv_info->dsc;

	}



	if (msm_is_mode_seamless(drm_mode))

		dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_SEAMLESS;

	if (msm_is_mode_dynamic_fps(drm_mode))
@@ -341,6 +346,8 @@ static bool dsi_bridge_mode_fixup(struct drm_bridge *bridge, 
	/* propagate the private info to the adjusted_mode derived dsi mode */

	dsi_mode.priv_info = panel_dsi_mode->priv_info;

	dsi_mode.dsi_mode_flags = panel_dsi_mode->dsi_mode_flags;

	dsi_mode.timing.dsc_enabled = dsi_mode.priv_info->dsc_enabled;

	dsi_mode.timing.dsc = &dsi_mode.priv_info->dsc;



	rc = dsi_display_validate_mode(c_bridge->display, &dsi_mode,

			DSI_VALIDATE_FLAG_ALLOW_ADJUST);
@@ -354,6 +361,9 @@ static bool dsi_bridge_mode_fixup(struct drm_bridge *bridge, 


		convert_to_dsi_mode(&crtc_state->crtc->state->mode,

							&cur_dsi_mode);

		cur_dsi_mode.timing.dsc_enabled =

				dsi_mode.priv_info->dsc_enabled;

		cur_dsi_mode.timing.dsc = &dsi_mode.priv_info->dsc;

		rc = dsi_display_validate_mode_vrr(c_bridge->display,

					&cur_dsi_mode, &dsi_mode);

		if (rc)

drivers/gpu/drm/msm/dsi-staging/dsi_panel.c

+4 −1
Original line number Diff line number Diff line
@@ -2293,7 +2293,7 @@ static int dsi_panel_parse_phy_timing(struct dsi_display_mode *mode, 
		priv_info->phy_timing_len = len;

	};



	mode->pixel_clk_khz = (DSI_H_TOTAL(&mode->timing) *

	mode->pixel_clk_khz = (DSI_H_TOTAL_DSC(&mode->timing) *

			DSI_V_TOTAL(&mode->timing) *

			mode->timing.refresh_rate) / 1000;

	return rc;
@@ -2414,6 +2414,9 @@ static int dsi_panel_parse_dsc_params(struct dsi_display_mode *mode, 
	dsi_dsc_populate_static_param(&priv_info->dsc);

	dsi_dsc_pclk_param_calc(&priv_info->dsc, intf_width);



	mode->timing.dsc_enabled = true;

	mode->timing.dsc = &priv_info->dsc;



error:

	return rc;

}

drivers/gpu/drm/msm/dsi-staging/dsi_phy_timing_calc.c

+1 −1
Original line number Diff line number Diff line
@@ -668,7 +668,7 @@ int dsi_phy_hw_calculate_timing_params(struct dsi_phy_hw *phy, 
	struct phy_timing_ops *ops = phy->ops.timing_ops;



	memset(&desc, 0x0, sizeof(desc));

	h_total = DSI_H_TOTAL(mode);

	h_total = DSI_H_TOTAL_DSC(mode);

	v_total = DSI_V_TOTAL(mode);



	bpp = bits_per_pixel[host->dst_format];