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Commit c15d8b04 authored by Viswanadha Raju Thotakura's avatar Viswanadha Raju Thotakura Committed by Jigarkumar Zala
Browse files

msm: camera: CSIPHY: Correct register settings for CPHY mode 



For sensor to stream under CPHY mode 2 SYNC pattern needs to enable.
This change updates the appropriate register value to set/detect
two sync pattern before streaming data.

Change-Id: Ic3d256574ecb7bc52a1dbb1304d6209285151603
Signed-off-by: default avatarViswanadha Raju Thotakura <viswanad@codeaurora.org>
Signed-off-by: default avatarJigarkumar Zala <jzala@codeaurora.org>
parent 1d993caf

drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h

+1 −1
Original line number Diff line number Diff line
@@ -44,7 +44,7 @@ 
#define MAX_CSIPHY_CMN_REG_ARRAY    5



#define MAX_LANES             5

#define MAX_SETTINGS_PER_LANE 42

#define MAX_SETTINGS_PER_LANE 43



#define MAX_REGULATOR         5

#define CAMX_CSIPHY_DEV_NAME "cam-csiphy-driver"

drivers/media/platform/msm/camera/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_1_hwreg.h

+16 −10
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ struct csiphy_reg_parms_t csiphy_v1_1 = { 
	.csiphy_common_array_size = 5,

	.csiphy_reset_array_size = 5,

	.csiphy_2ph_config_array_size = 14,

	.csiphy_3ph_config_array_size = 42,

	.csiphy_3ph_config_array_size = 43,

};



struct csiphy_reg_t csiphy_common_reg_1_1[] = {
@@ -252,7 +252,7 @@ csiphy_reg_t csiphy_3ph_v1_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x0124, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x012C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0144, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0144, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x01CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0164, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -261,13 +261,14 @@ csiphy_reg_t csiphy_3ph_v1_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x015C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x09B0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0980, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x09B0, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x015C, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x09B0, 0x24, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x015C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0984, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0988, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x09AC, 0x55, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x01DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0164, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},

	},

	{

		{0x0344, 0xB6, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -296,7 +297,7 @@ csiphy_reg_t csiphy_3ph_v1_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x0324, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x032C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0344, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0344, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x03CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0364, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -305,13 +306,14 @@ csiphy_reg_t csiphy_3ph_v1_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x035C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0AB0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0A80, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0AB0, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x035C, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0AB0, 0x24, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x035C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0A84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0A88, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0AAC, 0x55, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x03DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0364, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},

	},

	{

		{0x0544, 0xB6, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -340,7 +342,7 @@ csiphy_reg_t csiphy_3ph_v1_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x0524, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x052C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0544, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0544, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x05CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0564, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -349,13 +351,14 @@ csiphy_reg_t csiphy_3ph_v1_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x055C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0BB0, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0B80, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0BB0, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x055C, 0x48, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0BB0, 0x24, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x055C, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0B84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0B88, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0BAC, 0x55, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x05DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0564, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},

	},

};
@@ -404,6 +407,7 @@ struct csiphy_reg_t 
		{0x09AC, 0x55, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x01DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0164, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0800, 0x02, 0x00, CSIPHY_DNP_PARAMS},

	},

	{

		{0x0344, 0xB6, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -448,6 +452,7 @@ struct csiphy_reg_t 
		{0x0AAC, 0x55, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x03DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0364, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0800, 0x02, 0x00, CSIPHY_DNP_PARAMS},

	},

	{

		{0x0544, 0xB6, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -492,6 +497,7 @@ struct csiphy_reg_t 
		{0x0BAC, 0x55, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x05DC, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0564, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},

	},

};