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Commit c11f2b15 authored by Diptanshu Jamgade's avatar Diptanshu Jamgade
Browse files

ARM: dts: msm: Update the dummy GDSCs with actual GDSCs 



Update the Trinket GDSCs by replacing the dummy nodes
with actual GDSC regulator driver. Also add support for
turing_mmu and mm_snoc_mmu GDSCs.

Change-Id: I76ac062c3f91ff7471f67cdf8836c07553c10ecf
Signed-off-by: default avatarDiptanshu Jamgade <djamgade@codeaurora.org>
parent 9f512d30

arch/arm64/boot/dts/qcom/trinket-gdsc.dtsi

+47 −11
Original line number Diff line number Diff line
@@ -14,50 +14,86 @@ 
&soc {

	/* GDSCs in Global CC */

	camss_cpp_gdsc: qcom,gdsc@14560bc {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "cam_cpp_gdsc";

		reg = <0x14560bc 0x4>;

		status = "disabled";

	};



	camss_top_gdsc: qcom,gdsc@145607c {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "camss_top_gdsc";

		reg = <0x145607c 0x4>;

		status = "disabled";

	};



	camss_vfe0_gdsc: qcom,gdsc@1454004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "camss_vfe0_gdsc";

		reg = <0x1454004 0x4>;

		status = "disabled";

	};



	camss_vfe1_gdsc: qcom,gdsc@145403c {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "camss_vfe1_gdsc";

		reg = <0x145403c 0x4>;

		status = "disabled";

	};



	ufs_phy_gdsc: qcom,gdsc@1445004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "ufs_phy_gdsc";

		reg = <0x1445004 0x4>;

		status = "disabled";

	};



	usb30_prim_gdsc: qcom,gdsc@141a004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "usb30_prim_gdsc";

		reg = <0x141a004 0x4>;

		status = "disabled";

	};



	hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@147d060 {

		compatible = "qcom,gdsc";

		regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc";

		reg = <0x147d060 0x4>;

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};



	hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@1480094 {

		compatible = "qcom,gdsc";

		regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc";

		reg = <0x1480094 0x4>;

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};



	hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc: qcom,gdsc@1480074 {

		compatible = "qcom,gdsc";

		regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc";

		reg = <0x1480074 0x4>;

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};



	hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc: qcom,gdsc@1480084 {

		compatible = "qcom,gdsc";

		regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc";

		reg = <0x1480084 0x4>;

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};



	/* GDSCs in Display CC */

	mdss_core_gdsc: qcom,gdsc@5f03000 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "mdss_core_gdsc";

		reg = <0x5f03000 0x4>;

		qcom,support-hw-trigger;
@@ -73,7 +109,7 @@ 
	};



	gpu_cx_gdsc: qcom,gdsc@599106c {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "gpu_cx_gdsc";

		reg = <0x599106c 0x4>;

		hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
@@ -84,7 +120,7 @@ 
	};



	gpu_gx_gdsc: qcom,gdsc@599100c {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "gpu_gx_gdsc";

		reg = <0x599100c 0x4>;

		status = "disabled";
@@ -92,14 +128,14 @@ 


	/* GDSCs in Video CC */

	vcodec0_gdsc: qcom,gdsc@5b00874 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "vcodec0_gdsc";

		reg = <0x5b00874 0x4>;

		status = "disabled";

	};



	venus_gdsc: qcom,gdsc@5b00814 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "venus_gdsc";

		reg = <0x5b00814 0x4>;

		status = "disabled";

arch/arm64/boot/dts/qcom/trinket.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -2152,6 +2152,22 @@ 
	status = "ok";

};



&hlos1_vote_turing_mmu_tbu1_gdsc {

	status = "ok";

};



&hlos1_vote_turing_mmu_tbu0_gdsc {

	status = "ok";

};



&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc {

	status = "ok";

};



&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc {

	status = "ok";

};



&mdss_core_gdsc {

	status = "ok";

};