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Commit c10e4aa7 authored by Marc Zyngier's avatar Marc Zyngier Committed by Greg Kroah-Hartman
Browse files

arm64: Move post_ttbr_update_workaround to C code 



Commit 95e3de3590e3 upstream.

We will soon need to invoke a CPU-specific function pointer after changing
page tables, so move post_ttbr_update_workaround out into C code to make
this possible.

Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent f91f1907

arch/arm64/include/asm/assembler.h

+0 −13
Original line number Diff line number Diff line
@@ -481,19 +481,6 @@ alternative_endif 
	mrs	\rd, sp_el0

	.endm



/*

 * Errata workaround post TTBRx_EL1 update.

 */

	.macro	post_ttbr_update_workaround

#ifdef CONFIG_CAVIUM_ERRATUM_27456

alternative_if ARM64_WORKAROUND_CAVIUM_27456

	ic	iallu

	dsb	nsh

	isb

alternative_else_nop_endif

#endif

	.endm



/**

 * Errata workaround prior to disable MMU. Insert an ISB immediately prior

 * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.

arch/arm64/kernel/entry.S

+1 −1
Original line number Diff line number Diff line
@@ -275,7 +275,7 @@ alternative_else_nop_endif 
	 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache

	 * corruption).

	 */

	post_ttbr_update_workaround

	bl	post_ttbr_update_workaround

	.endif

1:

	.if	\el != 0

arch/arm64/mm/context.c

+9 −0
Original line number Diff line number Diff line
@@ -235,6 +235,15 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) 
		cpu_switch_mm(mm->pgd, mm);

}



/* Errata workaround post TTBRx_EL1 update. */

asmlinkage void post_ttbr_update_workaround(void)

{

	asm(ALTERNATIVE("nop; nop; nop",

			"ic iallu; dsb nsh; isb",

			ARM64_WORKAROUND_CAVIUM_27456,

			CONFIG_CAVIUM_ERRATUM_27456));

}



static int asids_init(void)

{

	asid_bits = get_cpu_asid_bits();

arch/arm64/mm/proc.S

+1 −2
Original line number Diff line number Diff line
@@ -148,8 +148,7 @@ ENTRY(cpu_do_switch_mm) 
	isb

	msr	ttbr0_el1, x0			// now update TTBR0

	isb

	post_ttbr_update_workaround

	ret

	b	post_ttbr_update_workaround	// Back to C code...

ENDPROC(cpu_do_switch_mm)



	.pushsection ".idmap.text", "awx"