Merge "ARM: dts: msm: Add PCIe pin definitions for sdmshrike" (c0d9347a) · Commits · e / devices / android_kernel_oneplus_sm8150

arch/arm64/boot/dts/qcom/sdmshrike-pinctrl.dtsi

+120 −0

Original line number	Diff line number	Diff line
		@@ -1882,6 +1882,126 @@
		};
		};

		pcie0 {
		pcie0_clkreq_default: pcie0_clkreq_default {
		mux {
		pins = "gpio36";
		function = "pci_e0";
		};

		config {
		pins = "gpio36";
		drive-strength = <2>;
		bias-pull-up;
		};
		};

		pcie0_perst_default: pcie0_perst_default {
		mux {
		pins = "gpio35";
		function = "gpio";
		};

		config {
		pins = "gpio35";
		drive-strength = <2>;
		bias-pull-down;
		};
		};

		pcie0_wake_default: pcie0_wake_default {
		mux {
		pins = "gpio37";
		function = "gpio";
		};

		config {
		pins = "gpio37";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		pcie1 {
		pcie1_clkreq_default: pcie1_clkreq_default {
		mux {
		pins = "gpio103";
		function = "pci_e1";
		};

		config {
		pins = "gpio103";
		drive-strength = <2>;
		bias-pull-up;
		};
		};

		pcie1_perst_default: pcie1_perst_default {
		mux {
		pins = "gpio102";
		function = "gpio";
		};

		config {
		pins = "gpio102";
		drive-strength = <2>;
		bias-pull-down;
		};
		};

		pcie1_wake_default: pcie1_wake_default {
		mux {
		pins = "gpio104";
		function = "gpio";
		};

		config {
		pins = "gpio104";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		pcie_ep {
		pcie_ep_clkreq_default: pcie_ep_clkreq_default {
		mux {
		pins = "gpio103";
		function = "pci_e1";
		};
		config {
		pins = "gpio103";
		drive-strength = <2>;
		bias-disable;
		};
		};

		pcie_ep_perst_default: pcie_ep_perst_default {
		mux {
		pins = "gpio102";
		function = "gpio";
		};
		config {
		pins = "gpio102";
		drive-strength = <2>;
		bias-pull-down;
		};
		};

		pcie_ep_wake_default: pcie_ep_wake_default {
		mux {
		pins = "gpio104";
		function = "gpio";
		};
		config {
		pins = "gpio104";
		drive-strength = <2>;
		bias-disable;
		};
		};
		};

		/* SE12 UART-2wire pin mappings */
		qupv3_se12_2uart_pins: qupv3_se12_2uart_pins {
		qupv3_se12_2uart_active: qupv3_se12_2uart_active {