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Commit c0b4c660 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Move VLV/CHV prepare_pll later 



With DPIO powergating active on CHV, we can't even access the DPIO PLL
registers until the lane power state overrides have been enabled. That
will happen from the encoder .pre_pll_enable() hook, so move
chv_prepare_pll() to happen after that point, which puts it just before
chv_enable_pll() actually.

Do the same for VLV to avoid accumulating weird differences between the
platforms. Both platforms seem happy with the new arrangement.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarDeepak S <deepak.s@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 770effb1

drivers/gpu/drm/i915/intel_display.c

+5 −9
Original line number Diff line number Diff line
@@ -6001,13 +6001,6 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) 


	is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);



	if (!is_dsi) {

		if (IS_CHERRYVIEW(dev))

			chv_prepare_pll(intel_crtc, intel_crtc->config);

		else

			vlv_prepare_pll(intel_crtc, intel_crtc->config);

	}



	if (intel_crtc->config->has_dp_encoder)

		intel_dp_set_m_n(intel_crtc, M1_N1);
@@ -6031,11 +6024,14 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) 
			encoder->pre_pll_enable(encoder);



	if (!is_dsi) {

		if (IS_CHERRYVIEW(dev))

		if (IS_CHERRYVIEW(dev)) {

			chv_prepare_pll(intel_crtc, intel_crtc->config);

			chv_enable_pll(intel_crtc, intel_crtc->config);

		else

		} else {

			vlv_prepare_pll(intel_crtc, intel_crtc->config);

			vlv_enable_pll(intel_crtc, intel_crtc->config);

		}

	}



	for_each_encoder_on_crtc(dev, crtc, encoder)

		if (encoder->pre_enable)