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Commit c0a9f72c authored by Alex Smith's avatar Alex Smith Committed by Ralf Baechle
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irqchip: irq-mips-gic: Provide function to map GIC user section 



The GIC provides a "user-mode visible" section containing a mirror of
the counter registers which can be mapped into user memory. This will
be used by the VDSO time function implementations, so provide a
function to map it in.

When the GIC is not enabled in Kconfig a dummy inline version of this
function is provided, along with "#define gic_present 0", so that we
don't have to litter the VDSO code with ifdefs.

[markos.chandras@imgtec.com:
  - Move mapping code to arch/mips/kernel/vdso.c and use a resource
    type to get the GIC usermode information
  - Avoid renaming function arguments and use __gic_base_addr to hold
    the base GIC address prior to ioremap.]
[ralf@linux-mips.org: Fix up gic_get_usm_range() to compile and make inline
again.]

Signed-off-by: default avatarAlex Smith <alex.smith@imgtec.com>
Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Alex Smith <alex.smith@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/11281/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent ebb5e78c

drivers/irqchip/irq-mips-gic.c

+14 −0
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ struct gic_pcpu_mask { 
	DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS);

};



static unsigned long __gic_base_addr;

static void __iomem *gic_base;

static struct gic_pcpu_mask pcpu_masks[NR_CPUS];

static DEFINE_SPINLOCK(gic_lock);
@@ -301,6 +302,17 @@ int gic_get_c0_fdc_int(void) 
				  GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC));

}



int gic_get_usm_range(struct resource *gic_usm_res)

{

	if (!gic_present)

		return -1;



	gic_usm_res->start = __gic_base_addr + USM_VISIBLE_SECTION_OFS;

	gic_usm_res->end = gic_usm_res->start + (USM_VISIBLE_SECTION_SIZE - 1);



	return 0;

}



static void gic_handle_shared_int(bool chained)

{

	unsigned int i, intr, virq, gic_reg_step = mips_cm_is64 ? 8 : 4;
@@ -798,6 +810,8 @@ static void __init __gic_init(unsigned long gic_base_addr, 
{

	unsigned int gicconfig;



	__gic_base_addr = gic_base_addr;



	gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size);



	gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));

include/linux/irqchip/mips-gic.h

+17 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#define __LINUX_IRQCHIP_MIPS_GIC_H



#include <linux/clocksource.h>

#include <linux/ioport.h>



#define GIC_MAX_INTRS			256
@@ -245,6 +246,8 @@ 
#define GIC_SHARED_TO_HWIRQ(x)	(GIC_SHARED_HWIRQ_BASE + (x))

#define GIC_HWIRQ_TO_SHARED(x)	((x) - GIC_SHARED_HWIRQ_BASE)



#ifdef CONFIG_MIPS_GIC



extern unsigned int gic_present;



extern void gic_init(unsigned long gic_base_addr,
@@ -264,4 +267,18 @@ extern unsigned int plat_ipi_resched_int_xlate(unsigned int); 
extern int gic_get_c0_compare_int(void);

extern int gic_get_c0_perfcount_int(void);

extern int gic_get_c0_fdc_int(void);

extern int gic_get_usm_range(struct resource *gic_usm_res);



#else /* CONFIG_MIPS_GIC */



#define gic_present	0



static inline int gic_get_usm_range(struct resource *gic_usm_res)

{

	/* Shouldn't be called. */

	return -1;

}



#endif /* CONFIG_MIPS_GIC */



#endif /* __LINUX_IRQCHIP_MIPS_GIC_H */