Merge "clk: qcom: Add sa6155 pcie support for virtual clock" (bf7d2ec9) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/clk/qcom/clk-virt-sm6150.c

+74 −0

Original line number	Diff line number	Diff line
		@@ -25,6 +25,8 @@ static struct virt_reset_map sm6150_gcc_virt_resets[] = {
		[GCC_USB20_SEC_BCR] = { "gcc_usb20_sec_master_clk" },
		[GCC_USB3_PHY_PRIM_SP0_BCR] = { "gcc_usb3_phy_prim_sp0_bcr" },
		[GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { "gcc_usb3phy_phy_prim_sp0_bcr" },
		[GCC_PCIE_0_BCR] = { "gcc_pcie_0_mstr_axi_clk" },
		[GCC_PCIE_0_PHY_BCR] = { "gcc_pcie_0_phy_bcr" },
		};

		static struct clk_virt gcc_qupv3_wrap0_s0_clk = {
		@@ -216,6 +218,69 @@ static struct clk_virt gcc_usb3_prim_phy_com_aux_clk = {
		},
		};

		static struct clk_virt gcc_pcie_0_pipe_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_pcie_0_pipe_clk",
		},
		};

		static struct clk_virt gcc_pcie_0_aux_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_pcie_0_aux_clk",
		},
		};

		static struct clk_virt gcc_pcie_0_cfg_ahb_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_pcie_0_cfg_ahb_clk",
		},
		};

		static struct clk_virt gcc_pcie_0_mstr_axi_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_pcie_0_mstr_axi_clk",
		},
		};

		static struct clk_virt gcc_pcie_0_slv_axi_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_pcie_0_slv_axi_clk",
		},
		};

		static struct clk_virt gcc_pcie_0_clkref_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_pcie_0_clkref_en",
		},
		};

		static struct clk_virt gcc_pcie_0_slv_q2a_axi_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_pcie_0_slv_q2a_axi_clk",
		},
		};

		static struct clk_virt gcc_pcie0_phy_refgen_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_pcie0_phy_refgen_clk",
		},
		};

		static struct clk_virt gcc_pcie_phy_aux_clk = {
		.hw.init = &(struct clk_init_data) {
		.ops = &clk_virt_ops,
		.name = "gcc_pcie_phy_aux_clk",
		},
		};

		static struct clk_hw *sm6150_gcc_virt_clocks[] = {
		[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.hw,
		[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.hw,
		@@ -244,6 +309,15 @@ static struct clk_hw *sm6150_gcc_virt_clocks[] = {
		[GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.hw,
		[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.hw,
		[GCC_AHB2PHY_WEST_CLK] = &gcc_ahb2phy_west_clk.hw,
		[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.hw,
		[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.hw,
		[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.hw,
		[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.hw,
		[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.hw,
		[GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.hw,
		[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.hw,
		[GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.hw,
		[GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.hw,
		};

		const struct clk_virt_desc clk_virt_sm6150_gcc = {