Loading drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c +16 −1 Original line number Diff line number Diff line Loading @@ -89,7 +89,8 @@ static void drm_mode_to_intf_timing_params( */ timing->width = mode->hdisplay; /* active width */ if (vid_enc->base.comp_type == MSM_DISPLAY_COMPRESSION_DSC) { if (phys_enc->hw_intf->cap->type != INTF_DP && vid_enc->base.comp_type == MSM_DISPLAY_COMPRESSION_DSC) { comp_ratio = vid_enc->base.comp_ratio; if (comp_ratio == MSM_DISPLAY_COMPRESSION_RATIO_2_TO_1) timing->width = DIV_ROUND_UP(timing->width, 2); Loading Loading @@ -130,6 +131,20 @@ static void drm_mode_to_intf_timing_params( timing->wide_bus_en = vid_enc->base.wide_bus_en; /* * for DP, divide the horizonal parameters by 2 when * widebus or compression is enabled, irrespective of * compression ratio */ if (phys_enc->hw_intf->cap->type == INTF_DP && (timing->wide_bus_en || vid_enc->base.comp_ratio)) { timing->width = timing->width >> 1; timing->xres = timing->xres >> 1; timing->h_back_porch = timing->h_back_porch >> 1; timing->h_front_porch = timing->h_front_porch >> 1; timing->hsync_pulse_width = timing->hsync_pulse_width >> 1; } /* * For edp only: * DISPLAY_V_START = (VBP * HCYCLE) + HBP Loading Loading
drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c +16 −1 Original line number Diff line number Diff line Loading @@ -89,7 +89,8 @@ static void drm_mode_to_intf_timing_params( */ timing->width = mode->hdisplay; /* active width */ if (vid_enc->base.comp_type == MSM_DISPLAY_COMPRESSION_DSC) { if (phys_enc->hw_intf->cap->type != INTF_DP && vid_enc->base.comp_type == MSM_DISPLAY_COMPRESSION_DSC) { comp_ratio = vid_enc->base.comp_ratio; if (comp_ratio == MSM_DISPLAY_COMPRESSION_RATIO_2_TO_1) timing->width = DIV_ROUND_UP(timing->width, 2); Loading Loading @@ -130,6 +131,20 @@ static void drm_mode_to_intf_timing_params( timing->wide_bus_en = vid_enc->base.wide_bus_en; /* * for DP, divide the horizonal parameters by 2 when * widebus or compression is enabled, irrespective of * compression ratio */ if (phys_enc->hw_intf->cap->type == INTF_DP && (timing->wide_bus_en || vid_enc->base.comp_ratio)) { timing->width = timing->width >> 1; timing->xres = timing->xres >> 1; timing->h_back_porch = timing->h_back_porch >> 1; timing->h_front_porch = timing->h_front_porch >> 1; timing->hsync_pulse_width = timing->hsync_pulse_width >> 1; } /* * For edp only: * DISPLAY_V_START = (VBP * HCYCLE) + HBP Loading