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Commit bec36eca authored by Paul Mundt's avatar Paul Mundt
Browse files

sh: hd64461: Fix up I/O base register offsets. 



hd64461 is mapped in a fixed location, so the I/O base itself is fairly
meaningless as a configuration item. Additionally, this makes it
impossible to share hd64461 code alongside generic drivers (in the case
of sh_dac_audio), so simply make it commonly defined and permit the
mach_is_foo() logic to work out the proper semantics.

Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 9304d0cc

arch/sh/cchips/Kconfig

+0 −5
Original line number Diff line number Diff line
@@ -34,11 +34,6 @@ config HD64461_IRQ 


	  Do not change this unless you know what you are doing.



config HD64461_IOBASE

	hex "HD64461 start address"

	depends on HD64461

	default "0xb0000000"



config HD64461_ENABLER

	bool "HD64461 PCMCIA enabler"

	depends on HD64461

arch/sh/include/asm/hd64461.h

+74 −72
Original line number Diff line number Diff line
@@ -13,13 +13,15 @@ 
#define	HD64461_PCC_WINDOW	0x01000000



/* Area 6 - Slot 0 - memory and/or IO card */

#define	HD64461_PCC0_BASE	(CONFIG_HD64461_IOBASE + 0x8000000)

#define HD64461_IOBASE		0xb0000000

#define HD64461_IO_OFFSET(x)	(HD64461_IOBASE + (x))

#define	HD64461_PCC0_BASE	HD64461_IO_OFFSET(0x8000000)

#define	HD64461_PCC0_ATTR	(HD64461_PCC0_BASE)				/* 0xb80000000 */

#define	HD64461_PCC0_COMM	(HD64461_PCC0_BASE+HD64461_PCC_WINDOW)		/* 0xb90000000 */

#define	HD64461_PCC0_IO		(HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW)	/* 0xba0000000 */



/* Area 5 - Slot 1 - memory card only */

#define	HD64461_PCC1_BASE	(CONFIG_HD64461_IOBASE + 0x4000000)

#define	HD64461_PCC1_BASE	HD64461_IO_OFFSET(0x4000000)

#define	HD64461_PCC1_ATTR	(HD64461_PCC1_BASE)				/* 0xb4000000 */

#define	HD64461_PCC1_COMM	(HD64461_PCC1_BASE+HD64461_PCC_WINDOW)		/* 0xb5000000 */
@@ -41,19 +43,19 @@ 
#define	HD64461_STBCR_SURTST		0x0001



/* System Configuration Register */

#define	HD64461_SYSCR		(CONFIG_HD64461_IOBASE + 0x02)

#define	HD64461_SYSCR		HD64461_IO_OFFSET(0x02)



/* CPU Data Bus Control Register */

#define	HD64461_SCPUCR		(CONFIG_HD64461_IOBASE + 0x04)

#define	HD64461_SCPUCR		HD64461_IO_OFFSET(0x04)



/* Base Address Register */

#define	HD64461_LCDCBAR		(CONFIG_HD64461_IOBASE + 0x1000)

#define	HD64461_LCDCBAR		HD64461_IO_OFFSET(0x1000)



/* Line increment address */

#define	HD64461_LCDCLOR		(CONFIG_HD64461_IOBASE + 0x1002)

#define	HD64461_LCDCLOR		HD64461_IO_OFFSET(0x1002)



/* Controls LCD controller */

#define	HD64461_LCDCCR		(CONFIG_HD64461_IOBASE + 0x1004)

#define	HD64461_LCDCCR		HD64461_IO_OFFSET(0x1004)



/* LCCDR control bits */

#define	HD64461_LCDCCR_STBACK	0x0400	/* Standby Back */
@@ -64,30 +66,30 @@ 
#define	HD64461_LCDCCR_SPON	0x0010	/* Start Power On */



/* Controls LCD (1) */

#define	HD64461_LDR1		(CONFIG_HD64461_IOBASE + 0x1010)

#define	HD64461_LDR1		HD64461_IO_OFFSET(0x1010)

#define	HD64461_LDR1_DON	0x01	/* Display On */

#define	HD64461_LDR1_DINV	0x80	/* Display Invert */



/* Controls LCD (2) */

#define	HD64461_LDR2		(CONFIG_HD64461_IOBASE + 0x1012)

#define	HD64461_LDHNCR		(CONFIG_HD64461_IOBASE + 0x1014)	/* Number of horizontal characters */

#define	HD64461_LDHNSR		(CONFIG_HD64461_IOBASE + 0x1016)	/* Specify output start position + width of CL1 */

#define	HD64461_LDVNTR		(CONFIG_HD64461_IOBASE + 0x1018)	/* Specify total vertical lines */

#define	HD64461_LDVNDR		(CONFIG_HD64461_IOBASE + 0x101a)	/* specify number of display vertical lines */

#define	HD64461_LDVSPR		(CONFIG_HD64461_IOBASE + 0x101c)	/* specify vertical synchronization pos and AC nr */

#define	HD64461_LDR2		HD64461_IO_OFFSET(0x1012)

#define	HD64461_LDHNCR		HD64461_IO_OFFSET(0x1014)	/* Number of horizontal characters */

#define	HD64461_LDHNSR		HD64461_IO_OFFSET(0x1016)	/* Specify output start position + width of CL1 */

#define	HD64461_LDVNTR		HD64461_IO_OFFSET(0x1018)	/* Specify total vertical lines */

#define	HD64461_LDVNDR		HD64461_IO_OFFSET(0x101a)	/* specify number of display vertical lines */

#define	HD64461_LDVSPR		HD64461_IO_OFFSET(0x101c)	/* specify vertical synchronization pos and AC nr */



/* Controls LCD (3) */

#define	HD64461_LDR3		(CONFIG_HD64461_IOBASE + 0x101e)

#define	HD64461_LDR3		HD64461_IO_OFFSET(0x101e)



/* Palette Registers */

#define	HD64461_CPTWAR		(CONFIG_HD64461_IOBASE + 0x1030)	/* Color Palette Write Address Register */

#define	HD64461_CPTWDR		(CONFIG_HD64461_IOBASE + 0x1032)	/* Color Palette Write Data Register */

#define	HD64461_CPTRAR		(CONFIG_HD64461_IOBASE + 0x1034)	/* Color Palette Read Address Register */

#define	HD64461_CPTRDR		(CONFIG_HD64461_IOBASE + 0x1036)	/* Color Palette Read Data Register */

#define	HD64461_CPTWAR		HD64461_IO_OFFSET(0x1030)	/* Color Palette Write Address Register */

#define	HD64461_CPTWDR		HD64461_IO_OFFSET(0x1032)	/* Color Palette Write Data Register */

#define	HD64461_CPTRAR		HD64461_IO_OFFSET(0x1034)	/* Color Palette Read Address Register */

#define	HD64461_CPTRDR		HD64461_IO_OFFSET(0x1036)	/* Color Palette Read Data Register */



#define	HD64461_GRDOR		(CONFIG_HD64461_IOBASE + 0x1040)	/* Display Resolution Offset Register */

#define	HD64461_GRSCR		(CONFIG_HD64461_IOBASE + 0x1042)	/* Solid Color Register */

#define	HD64461_GRCFGR		(CONFIG_HD64461_IOBASE + 0x1044)	/* Accelerator Configuration Register */

#define	HD64461_GRDOR		HD64461_IO_OFFSET(0x1040)	/* Display Resolution Offset Register */

#define	HD64461_GRSCR		HD64461_IO_OFFSET(0x1042)	/* Solid Color Register */

#define	HD64461_GRCFGR		HD64461_IO_OFFSET(0x1044)	/* Accelerator Configuration Register */



#define	HD64461_GRCFGR_ACCSTATUS	0x10	/* Accelerator Status */

#define	HD64461_GRCFGR_ACCRESET		0x08	/* Accelerator Reset */
@@ -97,41 +99,41 @@ 
#define	HD64461_GRCFGR_COLORDEPTH8	0x01	/* Sets Colordepth 8 for Accelerator */



/* Line Drawing Registers */

#define	HD64461_LNSARH		(CONFIG_HD64461_IOBASE + 0x1046)	/* Line Start Address Register (H) */

#define	HD64461_LNSARL		(CONFIG_HD64461_IOBASE + 0x1048)	/* Line Start Address Register (L) */

#define	HD64461_LNAXLR		(CONFIG_HD64461_IOBASE + 0x104a)	/* Axis Pixel Length Register */

#define	HD64461_LNDGR		(CONFIG_HD64461_IOBASE + 0x104c)	/* Diagonal Register */

#define	HD64461_LNAXR		(CONFIG_HD64461_IOBASE + 0x104e)	/* Axial Register */

#define	HD64461_LNERTR		(CONFIG_HD64461_IOBASE + 0x1050)	/* Start Error Term Register */

#define	HD64461_LNMDR		(CONFIG_HD64461_IOBASE + 0x1052)	/* Line Mode Register */

#define	HD64461_LNSARH		HD64461_IO_OFFSET(0x1046)	/* Line Start Address Register (H) */

#define	HD64461_LNSARL		HD64461_IO_OFFSET(0x1048)	/* Line Start Address Register (L) */

#define	HD64461_LNAXLR		HD64461_IO_OFFSET(0x104a)	/* Axis Pixel Length Register */

#define	HD64461_LNDGR		HD64461_IO_OFFSET(0x104c)	/* Diagonal Register */

#define	HD64461_LNAXR		HD64461_IO_OFFSET(0x104e)	/* Axial Register */

#define	HD64461_LNERTR		HD64461_IO_OFFSET(0x1050)	/* Start Error Term Register */

#define	HD64461_LNMDR		HD64461_IO_OFFSET(0x1052)	/* Line Mode Register */



/* BitBLT Registers */

#define	HD64461_BBTSSARH	(CONFIG_HD64461_IOBASE + 0x1054)	/* Source Start Address Register (H) */

#define	HD64461_BBTSSARL	(CONFIG_HD64461_IOBASE + 0x1056)	/* Source Start Address Register (L) */

#define	HD64461_BBTDSARH	(CONFIG_HD64461_IOBASE + 0x1058)	/* Destination Start Address Register (H) */

#define	HD64461_BBTDSARL	(CONFIG_HD64461_IOBASE + 0x105a)	/* Destination Start Address Register (L) */

#define	HD64461_BBTDWR		(CONFIG_HD64461_IOBASE + 0x105c)	/* Destination Block Width Register */

#define	HD64461_BBTDHR		(CONFIG_HD64461_IOBASE + 0x105e)	/* Destination Block Height Register */

#define	HD64461_BBTPARH		(CONFIG_HD64461_IOBASE + 0x1060)	/* Pattern Start Address Register (H) */

#define	HD64461_BBTPARL		(CONFIG_HD64461_IOBASE + 0x1062)	/* Pattern Start Address Register (L) */

#define	HD64461_BBTMARH		(CONFIG_HD64461_IOBASE + 0x1064)	/* Mask Start Address Register (H) */

#define	HD64461_BBTMARL		(CONFIG_HD64461_IOBASE + 0x1066)	/* Mask Start Address Register (L) */

#define	HD64461_BBTROPR		(CONFIG_HD64461_IOBASE + 0x1068)	/* ROP Register */

#define	HD64461_BBTMDR		(CONFIG_HD64461_IOBASE + 0x106a)	/* BitBLT Mode Register */

#define	HD64461_BBTSSARH	HD64461_IO_OFFSET(0x1054)	/* Source Start Address Register (H) */

#define	HD64461_BBTSSARL	HD64461_IO_OFFSET(0x1056)	/* Source Start Address Register (L) */

#define	HD64461_BBTDSARH	HD64461_IO_OFFSET(0x1058)	/* Destination Start Address Register (H) */

#define	HD64461_BBTDSARL	HD64461_IO_OFFSET(0x105a)	/* Destination Start Address Register (L) */

#define	HD64461_BBTDWR		HD64461_IO_OFFSET(0x105c)	/* Destination Block Width Register */

#define	HD64461_BBTDHR		HD64461_IO_OFFSET(0x105e)	/* Destination Block Height Register */

#define	HD64461_BBTPARH		HD64461_IO_OFFSET(0x1060)	/* Pattern Start Address Register (H) */

#define	HD64461_BBTPARL		HD64461_IO_OFFSET(0x1062)	/* Pattern Start Address Register (L) */

#define	HD64461_BBTMARH		HD64461_IO_OFFSET(0x1064)	/* Mask Start Address Register (H) */

#define	HD64461_BBTMARL		HD64461_IO_OFFSET(0x1066)	/* Mask Start Address Register (L) */

#define	HD64461_BBTROPR		HD64461_IO_OFFSET(0x1068)	/* ROP Register */

#define	HD64461_BBTMDR		HD64461_IO_OFFSET(0x106a)	/* BitBLT Mode Register */



/* PC Card Controller Registers */

/* Maps to Physical Area 6 */

#define	HD64461_PCC0ISR		(CONFIG_HD64461_IOBASE + 0x2000)	/* socket 0 interface status */

#define	HD64461_PCC0GCR		(CONFIG_HD64461_IOBASE + 0x2002)	/* socket 0 general control */

#define	HD64461_PCC0CSCR	(CONFIG_HD64461_IOBASE + 0x2004)	/* socket 0 card status change */

#define	HD64461_PCC0CSCIER	(CONFIG_HD64461_IOBASE + 0x2006)	/* socket 0 card status change interrupt enable */

#define	HD64461_PCC0SCR		(CONFIG_HD64461_IOBASE + 0x2008)	/* socket 0 software control */

#define	HD64461_PCC0ISR		HD64461_IO_OFFSET(0x2000)	/* socket 0 interface status */

#define	HD64461_PCC0GCR		HD64461_IO_OFFSET(0x2002)	/* socket 0 general control */

#define	HD64461_PCC0CSCR	HD64461_IO_OFFSET(0x2004)	/* socket 0 card status change */

#define	HD64461_PCC0CSCIER	HD64461_IO_OFFSET(0x2006)	/* socket 0 card status change interrupt enable */

#define	HD64461_PCC0SCR		HD64461_IO_OFFSET(0x2008)	/* socket 0 software control */

/* Maps to Physical Area 5 */

#define	HD64461_PCC1ISR		(CONFIG_HD64461_IOBASE + 0x2010)	/* socket 1 interface status */

#define	HD64461_PCC1GCR		(CONFIG_HD64461_IOBASE + 0x2012)	/* socket 1 general control */

#define	HD64461_PCC1CSCR	(CONFIG_HD64461_IOBASE + 0x2014)	/* socket 1 card status change */

#define	HD64461_PCC1CSCIER	(CONFIG_HD64461_IOBASE + 0x2016)	/* socket 1 card status change interrupt enable */

#define	HD64461_PCC1SCR		(CONFIG_HD64461_IOBASE + 0x2018)	/* socket 1 software control */

#define	HD64461_PCC1ISR		HD64461_IO_OFFSET(0x2010)	/* socket 1 interface status */

#define	HD64461_PCC1GCR		HD64461_IO_OFFSET(0x2012)	/* socket 1 general control */

#define	HD64461_PCC1CSCR	HD64461_IO_OFFSET(0x2014)	/* socket 1 card status change */

#define	HD64461_PCC1CSCIER	HD64461_IO_OFFSET(0x2016)	/* socket 1 card status change interrupt enable */

#define	HD64461_PCC1SCR		HD64461_IO_OFFSET(0x2018)	/* socket 1 software control */



/* PCC Interface Status Register */

#define	HD64461_PCCISR_READY		0x80	/* card ready */
@@ -189,41 +191,41 @@ 
#define	HD64461_PCCSCR_SWP		0x01	/* write protect */



/* PCC0 Output Pins Control Register */

#define	HD64461_P0OCR		(CONFIG_HD64461_IOBASE + 0x202a)

#define	HD64461_P0OCR		HD64461_IO_OFFSET(0x202a)



/* PCC1 Output Pins Control Register */

#define	HD64461_P1OCR		(CONFIG_HD64461_IOBASE + 0x202c)

#define	HD64461_P1OCR		HD64461_IO_OFFSET(0x202c)



/* PC Card General Control Register */

#define	HD64461_PGCR		(CONFIG_HD64461_IOBASE + 0x202e)

#define	HD64461_PGCR		HD64461_IO_OFFSET(0x202e)



/* Port Control Registers */

#define	HD64461_GPACR		(CONFIG_HD64461_IOBASE + 0x4000)	/* Port A - Handles IRDA/TIMER */

#define	HD64461_GPBCR		(CONFIG_HD64461_IOBASE + 0x4002)	/* Port B - Handles UART */

#define	HD64461_GPCCR		(CONFIG_HD64461_IOBASE + 0x4004)	/* Port C - Handles PCMCIA 1 */

#define	HD64461_GPDCR		(CONFIG_HD64461_IOBASE + 0x4006)	/* Port D - Handles PCMCIA 1 */

#define	HD64461_GPACR		HD64461_IO_OFFSET(0x4000)	/* Port A - Handles IRDA/TIMER */

#define	HD64461_GPBCR		HD64461_IO_OFFSET(0x4002)	/* Port B - Handles UART */

#define	HD64461_GPCCR		HD64461_IO_OFFSET(0x4004)	/* Port C - Handles PCMCIA 1 */

#define	HD64461_GPDCR		HD64461_IO_OFFSET(0x4006)	/* Port D - Handles PCMCIA 1 */



/* Port Control Data Registers */

#define	HD64461_GPADR		(CONFIG_HD64461_IOBASE + 0x4010)	/* A */

#define	HD64461_GPBDR		(CONFIG_HD64461_IOBASE + 0x4012)	/* B */

#define	HD64461_GPCDR		(CONFIG_HD64461_IOBASE + 0x4014)	/* C */

#define	HD64461_GPDDR		(CONFIG_HD64461_IOBASE + 0x4016)	/* D */

#define	HD64461_GPADR		HD64461_IO_OFFSET(0x4010)	/* A */

#define	HD64461_GPBDR		HD64461_IO_OFFSET(0x4012)	/* B */

#define	HD64461_GPCDR		HD64461_IO_OFFSET(0x4014)	/* C */

#define	HD64461_GPDDR		HD64461_IO_OFFSET(0x4016)	/* D */



/* Interrupt Control Registers */

#define	HD64461_GPAICR		(CONFIG_HD64461_IOBASE + 0x4020)	/* A */

#define	HD64461_GPBICR		(CONFIG_HD64461_IOBASE + 0x4022)	/* B */

#define	HD64461_GPCICR		(CONFIG_HD64461_IOBASE + 0x4024)	/* C */

#define	HD64461_GPDICR		(CONFIG_HD64461_IOBASE + 0x4026)	/* D */

#define	HD64461_GPAICR		HD64461_IO_OFFSET(0x4020)	/* A */

#define	HD64461_GPBICR		HD64461_IO_OFFSET(0x4022)	/* B */

#define	HD64461_GPCICR		HD64461_IO_OFFSET(0x4024)	/* C */

#define	HD64461_GPDICR		HD64461_IO_OFFSET(0x4026)	/* D */



/* Interrupt Status Registers */

#define	HD64461_GPAISR		(CONFIG_HD64461_IOBASE + 0x4040)	/* A */

#define	HD64461_GPBISR		(CONFIG_HD64461_IOBASE + 0x4042)	/* B */

#define	HD64461_GPCISR		(CONFIG_HD64461_IOBASE + 0x4044)	/* C */

#define	HD64461_GPDISR		(CONFIG_HD64461_IOBASE + 0x4046)	/* D */

#define	HD64461_GPAISR		HD64461_IO_OFFSET(0x4040)	/* A */

#define	HD64461_GPBISR		HD64461_IO_OFFSET(0x4042)	/* B */

#define	HD64461_GPCISR		HD64461_IO_OFFSET(0x4044)	/* C */

#define	HD64461_GPDISR		HD64461_IO_OFFSET(0x4046)	/* D */



/* Interrupt Request Register & Interrupt Mask Register */

#define	HD64461_NIRR		(CONFIG_HD64461_IOBASE + 0x5000)

#define	HD64461_NIMR		(CONFIG_HD64461_IOBASE + 0x5002)

#define	HD64461_NIRR		HD64461_IO_OFFSET(0x5000)

#define	HD64461_NIMR		HD64461_IO_OFFSET(0x5002)



#define	HD64461_IRQBASE		OFFCHIP_IRQ_BASE

#define	OFFCHIP_IRQ_BASE	64