Commit beb3e182 authored May 30, 2018 by Deepak Katragadda

clk: qcom: npucc-sm8150: Minor change to the CRC enable sequence



As part of the CRC enable sequence for the npu_cc_cal_dp_clk_src
RCG, the clock driver currently sets the RCGs rate to the VDD_MIN
frequency. However, that's not a corner that's supported on all
versions of the target. Set the RCG to the lowest supported
frequency instead.

Change-Id: I2c318a2b5870fc7ab2ea1481235725fc4eb9a7d0
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>

parent 9ee89464

drivers/clk/qcom/npucc-sm8150.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -603,9 +603,9 @@ static int enable_npu_crc(struct regmap *regmap)
		{
		int ret = 0;

		/* Set npu_cc_cal_cp_clk to a safe frequency */
		/* Set npu_cc_cal_cp_clk to the lowest supported frequency */
		clk_set_rate(npu_cc_cal_dp_clk.clkr.hw.clk,
		npu_cc_cal_dp_clk_src.clkr.hw.init->rate_max[VDD_MIN]);
		clk_round_rate(npu_cc_cal_dp_clk_src.clkr.hw.clk, 1));
		/* Turn on the NPU GDSC */
		ret = regulator_enable(vdd_gdsc);
		if (ret) {