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Commit bea8e86c authored by John Youn's avatar John Youn Committed by Felipe Balbi
Browse files

usb: dwc2: Declare the core params struct statically 



This makes it consistent with the hw_params struct and simplifies the
memory management for future refactoring. Fix up usage in all files.

Signed-off-by: default avatarJohn Youn <johnyoun@synopsys.com>
Signed-off-by: default avatarFelipe Balbi <felipe.balbi@linux.intel.com>
parent 323230ef

drivers/usb/dwc2/core.c

+6 −6
Original line number Diff line number Diff line
@@ -135,7 +135,7 @@ int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore) 
	u32 pcgcctl;

	int ret = 0;



	if (!hsotg->core_params->hibernation)

	if (!hsotg->params.hibernation)

		return -ENOTSUPP;



	pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
@@ -188,7 +188,7 @@ int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg) 
	u32 pcgcctl;

	int ret = 0;



	if (!hsotg->core_params->hibernation)

	if (!hsotg->params.hibernation)

		return -ENOTSUPP;



	/* Backup all registers */
@@ -541,7 +541,7 @@ void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg) 
	addr = hsotg->regs + HAINTMSK;

	dev_dbg(hsotg->dev, "HAINTMSK	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));

	if (hsotg->core_params->dma_desc_enable > 0) {

	if (hsotg->params.dma_desc_enable > 0) {

		addr = hsotg->regs + HFLBADDR;

		dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",

			(unsigned long)addr, dwc2_readl(addr));
@@ -551,7 +551,7 @@ void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg) 
	dev_dbg(hsotg->dev, "HPRT0	 @0x%08lX : 0x%08X\n",

		(unsigned long)addr, dwc2_readl(addr));



	for (i = 0; i < hsotg->core_params->host_channels; i++) {

	for (i = 0; i < hsotg->params.host_channels; i++) {

		dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);

		addr = hsotg->regs + HCCHAR(i);

		dev_dbg(hsotg->dev, "HCCHAR	 @0x%08lX : 0x%08X\n",
@@ -571,7 +571,7 @@ void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg) 
		addr = hsotg->regs + HCDMA(i);

		dev_dbg(hsotg->dev, "HCDMA	 @0x%08lX : 0x%08X\n",

			(unsigned long)addr, dwc2_readl(addr));

		if (hsotg->core_params->dma_desc_enable > 0) {

		if (hsotg->params.dma_desc_enable > 0) {

			addr = hsotg->regs + HCDMAB(i);

			dev_dbg(hsotg->dev, "HCDMAB	 @0x%08lX : 0x%08X\n",

				(unsigned long)addr, dwc2_readl(addr));
@@ -753,7 +753,7 @@ bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host) 


u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg)

{

	return hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103;

	return hsotg->params.otg_ver == 1 ? 0x0200 : 0x0103;

}



bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)

drivers/usb/dwc2/core.h

+1 −1
Original line number Diff line number Diff line
@@ -850,7 +850,7 @@ struct dwc2_hsotg { 
	/** Params detected from hardware */

	struct dwc2_hw_params hw_params;

	/** Params to actually use */

	struct dwc2_core_params *core_params;

	struct dwc2_core_params params;

	enum usb_otg_state op_state;

	enum usb_dr_mode dr_mode;

	unsigned int hcd_enabled:1;

drivers/usb/dwc2/core_intr.c

+3 −3
Original line number Diff line number Diff line
@@ -159,9 +159,9 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) 
			" ++OTG Interrupt: Session Request Success Status Change++\n");

		gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);

		if (gotgctl & GOTGCTL_SESREQSCS) {

			if (hsotg->core_params->phy_type ==

			if (hsotg->params.phy_type ==

					DWC2_PHY_TYPE_PARAM_FS

			    && hsotg->core_params->i2c_enable > 0) {

			    && hsotg->params.i2c_enable > 0) {

				hsotg->srp_success = 1;

			} else {

				/* Clear Session Request */
@@ -370,7 +370,7 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg) 
		/* Change to L0 state */

		hsotg->lx_state = DWC2_L0;

	} else {

		if (hsotg->core_params->hibernation)

		if (hsotg->params.hibernation)

			return;



		if (hsotg->lx_state != DWC2_L1) {

drivers/usb/dwc2/gadget.c

+1 −1
Original line number Diff line number Diff line
@@ -2557,7 +2557,7 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, 
		GINTSTS_USBSUSP | GINTSTS_WKUPINT |

		GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;



	if (hsotg->core_params->external_id_pin_ctl <= 0)

	if (hsotg->params.external_id_pin_ctl <= 0)

		intmsk |= GINTSTS_CONIDSTSCHNG;



	dwc2_writel(intmsk, hsotg->regs + GINTMSK);

drivers/usb/dwc2/hcd.c

+95 −95
Original line number Diff line number Diff line
@@ -79,9 +79,9 @@ static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg) 
	/* Enable the interrupts in the GINTMSK */

	intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;



	if (hsotg->core_params->dma_enable <= 0)

	if (hsotg->params.dma_enable <= 0)

		intmsk |= GINTSTS_RXFLVL;

	if (hsotg->core_params->external_id_pin_ctl <= 0)

	if (hsotg->params.external_id_pin_ctl <= 0)

		intmsk |= GINTSTS_CONIDSTSCHNG;



	intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP |
@@ -100,8 +100,8 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) 


	if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&

	     hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&

	     hsotg->core_params->ulpi_fs_ls > 0) ||

	    hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {

	     hsotg->params.ulpi_fs_ls > 0) ||

	    hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {

		/* Full speed PHY */

		val = HCFG_FSLSPCLKSEL_48_MHZ;

	} else {
@@ -152,7 +152,7 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 
	if (dwc2_is_host_mode(hsotg))

		dwc2_init_fs_ls_pclk_sel(hsotg);



	if (hsotg->core_params->i2c_enable > 0) {

	if (hsotg->params.i2c_enable > 0) {

		dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");



		/* Program GUSBCFG.OtgUtmiFsSel to I2C */
@@ -189,20 +189,20 @@ static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 
	 * so only program the first time. Do a soft reset immediately after

	 * setting phyif.

	 */

	switch (hsotg->core_params->phy_type) {

	switch (hsotg->params.phy_type) {

	case DWC2_PHY_TYPE_PARAM_ULPI:

		/* ULPI interface */

		dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");

		usbcfg |= GUSBCFG_ULPI_UTMI_SEL;

		usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);

		if (hsotg->core_params->phy_ulpi_ddr > 0)

		if (hsotg->params.phy_ulpi_ddr > 0)

			usbcfg |= GUSBCFG_DDRSEL;

		break;

	case DWC2_PHY_TYPE_PARAM_UTMI:

		/* UTMI+ interface */

		dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");

		usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);

		if (hsotg->core_params->phy_utmi_width == 16)

		if (hsotg->params.phy_utmi_width == 16)

			usbcfg |= GUSBCFG_PHYIF16;

		break;

	default:
@@ -230,8 +230,8 @@ static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 
	u32 usbcfg;

	int retval = 0;



	if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL &&

	    hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {

	if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL &&

	    hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {

		/* If FS mode with FS PHY */

		retval = dwc2_fs_phy_init(hsotg, select_phy);

		if (retval)
@@ -245,7 +245,7 @@ static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 


	if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&

	    hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&

	    hsotg->core_params->ulpi_fs_ls > 0) {

	    hsotg->params.ulpi_fs_ls > 0) {

		dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");

		usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);

		usbcfg |= GUSBCFG_ULPI_FS_LS;
@@ -272,9 +272,9 @@ static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) 


	case GHWCFG2_INT_DMA_ARCH:

		dev_dbg(hsotg->dev, "Internal DMA Mode\n");

		if (hsotg->core_params->ahbcfg != -1) {

		if (hsotg->params.ahbcfg != -1) {

			ahbcfg &= GAHBCFG_CTRL_MASK;

			ahbcfg |= hsotg->core_params->ahbcfg &

			ahbcfg |= hsotg->params.ahbcfg &

				  ~GAHBCFG_CTRL_MASK;

		}

		break;
@@ -286,20 +286,20 @@ static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) 
	}



	dev_dbg(hsotg->dev, "dma_enable:%d dma_desc_enable:%d\n",

		hsotg->core_params->dma_enable,

		hsotg->core_params->dma_desc_enable);

		hsotg->params.dma_enable,

		hsotg->params.dma_desc_enable);



	if (hsotg->core_params->dma_enable > 0) {

		if (hsotg->core_params->dma_desc_enable > 0)

	if (hsotg->params.dma_enable > 0) {

		if (hsotg->params.dma_desc_enable > 0)

			dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n");

		else

			dev_dbg(hsotg->dev, "Using Buffer DMA mode\n");

	} else {

		dev_dbg(hsotg->dev, "Using Slave mode\n");

		hsotg->core_params->dma_desc_enable = 0;

		hsotg->params.dma_desc_enable = 0;

	}



	if (hsotg->core_params->dma_enable > 0)

	if (hsotg->params.dma_enable > 0)

		ahbcfg |= GAHBCFG_DMA_EN;



	dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
@@ -316,10 +316,10 @@ static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) 


	switch (hsotg->hw_params.op_mode) {

	case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:

		if (hsotg->core_params->otg_cap ==

		if (hsotg->params.otg_cap ==

				DWC2_CAP_PARAM_HNP_SRP_CAPABLE)

			usbcfg |= GUSBCFG_HNPCAP;

		if (hsotg->core_params->otg_cap !=

		if (hsotg->params.otg_cap !=

				DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)

			usbcfg |= GUSBCFG_SRPCAP;

		break;
@@ -327,7 +327,7 @@ static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) 
	case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:

	case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:

	case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:

		if (hsotg->core_params->otg_cap !=

		if (hsotg->params.otg_cap !=

				DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)

			usbcfg |= GUSBCFG_SRPCAP;

		break;
@@ -390,7 +390,7 @@ static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) 
 */

static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)

{

	struct dwc2_core_params *params = hsotg->core_params;

	struct dwc2_core_params *params = &hsotg->params;

	struct dwc2_hw_params *hw = &hsotg->hw_params;

	u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;
@@ -449,7 +449,7 @@ static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg) 


static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)

{

	struct dwc2_core_params *params = hsotg->core_params;

	struct dwc2_core_params *params = &hsotg->params;

	u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;



	if (!params->enable_dynamic_fifo)
@@ -490,7 +490,7 @@ static void dwc2_config_fifos(struct dwc2_hsotg *hsotg) 
	dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",

		dwc2_readl(hsotg->regs + HPTXFSIZ));



	if (hsotg->core_params->en_multiple_tx_fifo > 0 &&

	if (hsotg->params.en_multiple_tx_fifo > 0 &&

	    hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) {

		/*

		 * Global DFIFOCFG calculation for Host mode -
@@ -598,7 +598,7 @@ static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 
				   struct dwc2_host_chan *chan)

{

#ifdef VERBOSE_DEBUG

	int num_channels = hsotg->core_params->host_channels;

	int num_channels = hsotg->params.host_channels;

	struct dwc2_qh *qh;

	u32 hcchar;

	u32 hcsplt;
@@ -741,7 +741,7 @@ static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg, 
	 * For Descriptor DMA mode core halts the channel on AHB error.

	 * Interrupt is not required.

	 */

	if (hsotg->core_params->dma_desc_enable <= 0) {

	if (hsotg->params.dma_desc_enable <= 0) {

		if (dbg_hc(chan))

			dev_vdbg(hsotg->dev, "desc DMA disabled\n");

		hcintmsk |= HCINTMSK_AHBERR;
@@ -774,7 +774,7 @@ static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg, 
{

	u32 intmsk;



	if (hsotg->core_params->dma_enable > 0) {

	if (hsotg->params.dma_enable > 0) {

		if (dbg_hc(chan))

			dev_vdbg(hsotg->dev, "DMA enabled\n");

		dwc2_hc_enable_dma_ints(hsotg, chan);
@@ -994,7 +994,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 


	/* No need to set the bit in DDMA for disabling the channel */

	/* TODO check it everywhere channel is disabled */

	if (hsotg->core_params->dma_desc_enable <= 0) {

	if (hsotg->params.dma_desc_enable <= 0) {

		if (dbg_hc(chan))

			dev_vdbg(hsotg->dev, "desc DMA disabled\n");

		hcchar |= HCCHAR_CHENA;
@@ -1004,7 +1004,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 
	}

	hcchar |= HCCHAR_CHDIS;



	if (hsotg->core_params->dma_enable <= 0) {

	if (hsotg->params.dma_enable <= 0) {

		if (dbg_hc(chan))

			dev_vdbg(hsotg->dev, "DMA not enabled\n");

		hcchar |= HCCHAR_CHENA;
@@ -1143,7 +1143,7 @@ static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg, 
		fifo_space = (dwc2_readl(hsotg->regs + HPTXSTS) &

			      TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT;

		bytes_in_fifo = sizeof(u32) *

				(hsotg->core_params->host_perio_tx_fifo_size -

				(hsotg->params.host_perio_tx_fifo_size -

				 fifo_space);



		/*
@@ -1339,8 +1339,8 @@ static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 
static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,

				   struct dwc2_host_chan *chan)

{

	u32 max_hc_xfer_size = hsotg->core_params->max_transfer_size;

	u16 max_hc_pkt_count = hsotg->core_params->max_packet_count;

	u32 max_hc_xfer_size = hsotg->params.max_transfer_size;

	u16 max_hc_pkt_count = hsotg->params.max_packet_count;

	u32 hcchar;

	u32 hctsiz = 0;

	u16 num_packets;
@@ -1350,7 +1350,7 @@ static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 
		dev_vdbg(hsotg->dev, "%s()\n", __func__);



	if (chan->do_ping) {

		if (hsotg->core_params->dma_enable <= 0) {

		if (hsotg->params.dma_enable <= 0) {

			if (dbg_hc(chan))

				dev_vdbg(hsotg->dev, "ping, no DMA\n");

			dwc2_hc_do_ping(hsotg, chan);
@@ -1478,7 +1478,7 @@ static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 
			 TSIZ_SC_MC_PID_SHIFT);

	}



	if (hsotg->core_params->dma_enable > 0) {

	if (hsotg->params.dma_enable > 0) {

		dwc2_writel((u32)chan->xfer_dma,

			    hsotg->regs + HCDMA(chan->hc_num));

		if (dbg_hc(chan))
@@ -1521,7 +1521,7 @@ static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 
	chan->xfer_started = 1;

	chan->requests++;



	if (hsotg->core_params->dma_enable <= 0 &&

	if (hsotg->params.dma_enable <= 0 &&

	    !chan->ep_is_in && chan->xfer_len > 0)

		/* Load OUT packet into the appropriate Tx FIFO */

		dwc2_hc_write_packet(hsotg, chan);
@@ -1799,12 +1799,12 @@ void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 
/* Must be called with interrupt disabled and spinlock held */

static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)

{

	int num_channels = hsotg->core_params->host_channels;

	int num_channels = hsotg->params.host_channels;

	struct dwc2_host_chan *channel;

	u32 hcchar;

	int i;



	if (hsotg->core_params->dma_enable <= 0) {

	if (hsotg->params.dma_enable <= 0) {

		/* Flush out any channel requests in slave mode */

		for (i = 0; i < num_channels; i++) {

			channel = hsotg->hc_ptr_array[i];
@@ -1840,9 +1840,9 @@ static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 
		channel->qh = NULL;

	}

	/* All channels have been freed, mark them available */

	if (hsotg->core_params->uframe_sched > 0) {

	if (hsotg->params.uframe_sched > 0) {

		hsotg->available_host_channels =

			hsotg->core_params->host_channels;

			hsotg->params.host_channels;

	} else {

		hsotg->non_periodic_channels = 0;

		hsotg->periodic_channels = 0;
@@ -2077,7 +2077,7 @@ static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 
	 * Free the QTD and clean up the associated QH. Leave the QH in the

	 * schedule if it has any remaining QTDs.

	 */

	if (hsotg->core_params->dma_desc_enable <= 0) {

	if (hsotg->params.dma_desc_enable <= 0) {

		u8 in_process = urb_qtd->in_process;



		dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
@@ -2185,13 +2185,13 @@ static int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) 


	/* Set ULPI External VBUS bit if needed */

	usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;

	if (hsotg->core_params->phy_ulpi_ext_vbus ==

	if (hsotg->params.phy_ulpi_ext_vbus ==

				DWC2_PHY_ULPI_EXTERNAL_VBUS)

		usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;



	/* Set external TS Dline pulsing bit if needed */

	usbcfg &= ~GUSBCFG_TERMSELDLPULSE;

	if (hsotg->core_params->ts_dline > 0)

	if (hsotg->params.ts_dline > 0)

		usbcfg |= GUSBCFG_TERMSELDLPULSE;



	dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
@@ -2230,10 +2230,10 @@ static int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) 
	/* Program the GOTGCTL register */

	otgctl = dwc2_readl(hsotg->regs + GOTGCTL);

	otgctl &= ~GOTGCTL_OTGVER;

	if (hsotg->core_params->otg_ver > 0)

	if (hsotg->params.otg_ver > 0)

		otgctl |= GOTGCTL_OTGVER;

	dwc2_writel(otgctl, hsotg->regs + GOTGCTL);

	dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver);

	dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->params.otg_ver);



	/* Clear the SRP success bit for FS-I2c */

	hsotg->srp_success = 0;
@@ -2277,7 +2277,7 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg) 


	/* Initialize Host Configuration Register */

	dwc2_init_fs_ls_pclk_sel(hsotg);

	if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) {

	if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL) {

		hcfg = dwc2_readl(hsotg->regs + HCFG);

		hcfg |= HCFG_FSLSSUPP;

		dwc2_writel(hcfg, hsotg->regs + HCFG);
@@ -2288,13 +2288,13 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg) 
	 * runtime. This bit needs to be programmed during initial configuration

	 * and its value must not be changed during runtime.

	 */

	if (hsotg->core_params->reload_ctl > 0) {

	if (hsotg->params.reload_ctl > 0) {

		hfir = dwc2_readl(hsotg->regs + HFIR);

		hfir |= HFIR_RLDCTRL;

		dwc2_writel(hfir, hsotg->regs + HFIR);

	}



	if (hsotg->core_params->dma_desc_enable > 0) {

	if (hsotg->params.dma_desc_enable > 0) {

		u32 op_mode = hsotg->hw_params.op_mode;



		if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
@@ -2306,7 +2306,7 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg) 
				"Hardware does not support descriptor DMA mode -\n");

			dev_err(hsotg->dev,

				"falling back to buffer DMA mode.\n");

			hsotg->core_params->dma_desc_enable = 0;

			hsotg->params.dma_desc_enable = 0;

		} else {

			hcfg = dwc2_readl(hsotg->regs + HCFG);

			hcfg |= HCFG_DESCDMA;
@@ -2332,12 +2332,12 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg) 
	otgctl &= ~GOTGCTL_HSTSETHNPEN;

	dwc2_writel(otgctl, hsotg->regs + GOTGCTL);



	if (hsotg->core_params->dma_desc_enable <= 0) {

	if (hsotg->params.dma_desc_enable <= 0) {

		int num_channels, i;

		u32 hcchar;



		/* Flush out any leftover queued requests */

		num_channels = hsotg->core_params->host_channels;

		num_channels = hsotg->params.host_channels;

		for (i = 0; i < num_channels; i++) {

			hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));

			hcchar &= ~HCCHAR_CHENA;
@@ -2399,9 +2399,9 @@ static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 
	hsotg->flags.d32 = 0;

	hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;



	if (hsotg->core_params->uframe_sched > 0) {

	if (hsotg->params.uframe_sched > 0) {

		hsotg->available_host_channels =

			hsotg->core_params->host_channels;

			hsotg->params.host_channels;

	} else {

		hsotg->non_periodic_channels = 0;

		hsotg->periodic_channels = 0;
@@ -2415,7 +2415,7 @@ static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 
				 hc_list_entry)

		list_del_init(&chan->hc_list_entry);



	num_channels = hsotg->core_params->host_channels;

	num_channels = hsotg->params.host_channels;

	for (i = 0; i < num_channels; i++) {

		chan = hsotg->hc_ptr_array[i];

		list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
@@ -2457,7 +2457,7 @@ static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 
			chan->do_ping = 0;

			chan->ep_is_in = 0;

			chan->data_pid_start = DWC2_HC_PID_SETUP;

			if (hsotg->core_params->dma_enable > 0)

			if (hsotg->params.dma_enable > 0)

				chan->xfer_dma = urb->setup_dma;

			else

				chan->xfer_buf = urb->setup_packet;
@@ -2484,7 +2484,7 @@ static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 
				chan->do_ping = 0;

			chan->data_pid_start = DWC2_HC_PID_DATA1;

			chan->xfer_len = 0;

			if (hsotg->core_params->dma_enable > 0)

			if (hsotg->params.dma_enable > 0)

				chan->xfer_dma = hsotg->status_buf_dma;

			else

				chan->xfer_buf = hsotg->status_buf;
@@ -2502,13 +2502,13 @@ static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 


	case USB_ENDPOINT_XFER_ISOC:

		chan->ep_type = USB_ENDPOINT_XFER_ISOC;

		if (hsotg->core_params->dma_desc_enable > 0)

		if (hsotg->params.dma_desc_enable > 0)

			break;



		frame_desc = &urb->iso_descs[qtd->isoc_frame_index];

		frame_desc->status = 0;



		if (hsotg->core_params->dma_enable > 0) {

		if (hsotg->params.dma_enable > 0) {

			chan->xfer_dma = urb->dma;

			chan->xfer_dma += frame_desc->offset +

					qtd->isoc_split_offset;
@@ -2690,7 +2690,7 @@ static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 
		!dwc2_hcd_is_pipe_in(&urb->pipe_info))

		urb->actual_length = urb->length;



	if (hsotg->core_params->dma_enable > 0)

	if (hsotg->params.dma_enable > 0)

		chan->xfer_dma = urb->dma + urb->actual_length;

	else

		chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
@@ -2715,7 +2715,7 @@ static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 
		 */

		chan->multi_count = dwc2_hb_mult(qh->maxp);



	if (hsotg->core_params->dma_desc_enable > 0) {

	if (hsotg->params.dma_desc_enable > 0) {

		chan->desc_list_addr = qh->desc_list_dma;

		chan->desc_list_sz = qh->desc_list_sz;

	}
@@ -2752,7 +2752,7 @@ enum dwc2_transaction_type dwc2_hcd_select_transactions( 
	while (qh_ptr != &hsotg->periodic_sched_ready) {

		if (list_empty(&hsotg->free_hc_list))

			break;

		if (hsotg->core_params->uframe_sched > 0) {

		if (hsotg->params.uframe_sched > 0) {

			if (hsotg->available_host_channels <= 1)

				break;

			hsotg->available_host_channels--;
@@ -2776,17 +2776,17 @@ enum dwc2_transaction_type dwc2_hcd_select_transactions( 
	 * schedule. Some free host channels may not be used if they are

	 * reserved for periodic transfers.

	 */

	num_channels = hsotg->core_params->host_channels;

	num_channels = hsotg->params.host_channels;

	qh_ptr = hsotg->non_periodic_sched_inactive.next;

	while (qh_ptr != &hsotg->non_periodic_sched_inactive) {

		if (hsotg->core_params->uframe_sched <= 0 &&

		if (hsotg->params.uframe_sched <= 0 &&

		    hsotg->non_periodic_channels >= num_channels -

						hsotg->periodic_channels)

			break;

		if (list_empty(&hsotg->free_hc_list))

			break;

		qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);

		if (hsotg->core_params->uframe_sched > 0) {

		if (hsotg->params.uframe_sched > 0) {

			if (hsotg->available_host_channels < 1)

				break;

			hsotg->available_host_channels--;
@@ -2808,7 +2808,7 @@ enum dwc2_transaction_type dwc2_hcd_select_transactions( 
		else

			ret_val = DWC2_TRANSACTION_ALL;



		if (hsotg->core_params->uframe_sched <= 0)

		if (hsotg->params.uframe_sched <= 0)

			hsotg->non_periodic_channels++;

	}
@@ -2847,8 +2847,8 @@ static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 
		list_move_tail(&chan->split_order_list_entry,

			       &hsotg->split_order);



	if (hsotg->core_params->dma_enable > 0) {

		if (hsotg->core_params->dma_desc_enable > 0) {

	if (hsotg->params.dma_enable > 0) {

		if (hsotg->params.dma_desc_enable > 0) {

			if (!chan->xfer_started ||

			    chan->ep_type == USB_ENDPOINT_XFER_ISOC) {

				dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
@@ -2957,7 +2957,7 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 
		 * The flag prevents any halts to get into the request queue in

		 * the middle of multiple high-bandwidth packets getting queued.

		 */

		if (hsotg->core_params->dma_enable <= 0 &&

		if (hsotg->params.dma_enable <= 0 &&

				qh->channel->multi_count > 1)

			hsotg->queuing_high_bandwidth = 1;
@@ -2976,7 +2976,7 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 
		 * controller automatically handles multiple packets for

		 * high-bandwidth transfers.

		 */

		if (hsotg->core_params->dma_enable > 0 || status == 0 ||

		if (hsotg->params.dma_enable > 0 || status == 0 ||

		    qh->channel->requests == qh->channel->multi_count) {

			qh_ptr = qh_ptr->next;

			/*
@@ -2993,7 +2993,7 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 


exit:

	if (no_queue_space || no_fifo_space ||

	    (hsotg->core_params->dma_enable <= 0 &&

	    (hsotg->params.dma_enable <= 0 &&

	     !list_empty(&hsotg->periodic_sched_assigned))) {

		/*

		 * May need to queue more transactions as the request
@@ -3073,7 +3073,7 @@ static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 
		tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);

		qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>

			    TXSTS_QSPCAVAIL_SHIFT;

		if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) {

		if (hsotg->params.dma_enable <= 0 && qspcavail == 0) {

			no_queue_space = 1;

			break;

		}
@@ -3106,7 +3106,7 @@ static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 
					hsotg->non_periodic_qh_ptr->next;

	} while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);



	if (hsotg->core_params->dma_enable <= 0) {

	if (hsotg->params.dma_enable <= 0) {

		tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);

		qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>

			    TXSTS_QSPCAVAIL_SHIFT;
@@ -3307,7 +3307,7 @@ static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 
	 * If hibernation is supported, Phy clock will be suspended

	 * after registers are backuped.

	 */

	if (!hsotg->core_params->hibernation) {

	if (!hsotg->params.hibernation) {

		/* Suspend the Phy Clock */

		pcgctl = dwc2_readl(hsotg->regs + PCGCTL);

		pcgctl |= PCGCTL_STOPPCLK;
@@ -3342,7 +3342,7 @@ static void dwc2_port_resume(struct dwc2_hsotg *hsotg) 
	 * If hibernation is supported, Phy clock is already resumed

	 * after registers restore.

	 */

	if (!hsotg->core_params->hibernation) {

	if (!hsotg->params.hibernation) {

		pcgctl = dwc2_readl(hsotg->regs + PCGCTL);

		pcgctl &= ~PCGCTL_STOPPCLK;

		dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
@@ -3569,7 +3569,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 
			port_status |= USB_PORT_STAT_TEST;

		/* USB_PORT_FEAT_INDICATOR unsupported always 0 */



		if (hsotg->core_params->dma_desc_fs_enable) {

		if (hsotg->params.dma_desc_fs_enable) {

			/*

			 * Enable descriptor DMA only if a full speed

			 * device is connected.
@@ -3583,7 +3583,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 
				u32 hcfg;



				dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");

				hsotg->core_params->dma_desc_enable = 1;

				hsotg->params.dma_desc_enable = 1;

				hcfg = dwc2_readl(hsotg->regs + HCFG);

				hcfg |= HCFG_DESCDMA;

				dwc2_writel(hcfg, hsotg->regs + HCFG);
@@ -3824,7 +3824,7 @@ void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 
	u32 p_tx_status;

	int i;



	num_channels = hsotg->core_params->host_channels;

	num_channels = hsotg->params.host_channels;

	dev_dbg(hsotg->dev, "\n");

	dev_dbg(hsotg->dev,

		"************************************************************\n");
@@ -4365,7 +4365,7 @@ static int _dwc2_hcd_suspend(struct usb_hcd *hcd) 
	if (!HCD_HW_ACCESSIBLE(hcd))

		goto unlock;



	if (!hsotg->core_params->hibernation)

	if (!hsotg->params.hibernation)

		goto skip_power_saving;



	/*
@@ -4417,7 +4417,7 @@ static int _dwc2_hcd_resume(struct usb_hcd *hcd) 
	if (hsotg->lx_state != DWC2_L2)

		goto unlock;



	if (!hsotg->core_params->hibernation) {

	if (!hsotg->params.hibernation) {

		hsotg->lx_state = DWC2_L0;

		goto unlock;

	}
@@ -4919,7 +4919,7 @@ static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 
		}

	}



	if (hsotg->core_params->dma_enable > 0) {

	if (hsotg->params.dma_enable > 0) {

		if (hsotg->status_buf) {

			dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,

					  hsotg->status_buf,
@@ -4999,16 +4999,16 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 
	hsotg->last_frame_num = HFNUM_MAX_FRNUM;



	/* Check if the bus driver or platform code has setup a dma_mask */

	if (hsotg->core_params->dma_enable > 0 &&

	if (hsotg->params.dma_enable > 0 &&

	    hsotg->dev->dma_mask == NULL) {

		dev_warn(hsotg->dev,

			 "dma_mask not set, disabling DMA\n");

		hsotg->core_params->dma_enable = 0;

		hsotg->core_params->dma_desc_enable = 0;

		hsotg->params.dma_enable = 0;

		hsotg->params.dma_desc_enable = 0;

	}



	/* Set device flags indicating whether the HCD supports DMA */

	if (hsotg->core_params->dma_enable > 0) {

	if (hsotg->params.dma_enable > 0) {

		if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)

			dev_warn(hsotg->dev, "can't set DMA mask\n");

		if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
@@ -5019,7 +5019,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 
	if (!hcd)

		goto error1;



	if (hsotg->core_params->dma_enable <= 0)

	if (hsotg->params.dma_enable <= 0)

		hcd->self.uses_dma = 0;



	hcd->has_tt = 1;
@@ -5067,7 +5067,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 
	 * in the controller. Initialize the channel descriptor array.

	 */

	INIT_LIST_HEAD(&hsotg->free_hc_list);

	num_channels = hsotg->core_params->host_channels;

	num_channels = hsotg->params.host_channels;

	memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));



	for (i = 0; i < num_channels; i++) {
@@ -5091,7 +5091,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 
	 * done after usb_add_hcd since that function allocates the DMA buffer

	 * pool.

	 */

	if (hsotg->core_params->dma_enable > 0)

	if (hsotg->params.dma_enable > 0)

		hsotg->status_buf = dma_alloc_coherent(hsotg->dev,

					DWC2_HCD_STATUS_BUF_SIZE,

					&hsotg->status_buf_dma, GFP_KERNEL);
@@ -5107,8 +5107,8 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 
	 * DMA mode.

	 * Alignment must be set to 512 bytes.

	 */

	if (hsotg->core_params->dma_desc_enable ||

	    hsotg->core_params->dma_desc_fs_enable) {

	if (hsotg->params.dma_desc_enable ||

	    hsotg->params.dma_desc_fs_enable) {

		hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc",

				sizeof(struct dwc2_hcd_dma_desc) *

				MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA,
@@ -5121,8 +5121,8 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 
			 * Disable descriptor dma mode since it will not be

			 * usable.

			 */

			hsotg->core_params->dma_desc_enable = 0;

			hsotg->core_params->dma_desc_fs_enable = 0;

			hsotg->params.dma_desc_enable = 0;

			hsotg->params.dma_desc_fs_enable = 0;

		}



		hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc",
@@ -5138,8 +5138,8 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 
			 * Disable descriptor dma mode since it will not be

			 * usable.

			 */

			hsotg->core_params->dma_desc_enable = 0;

			hsotg->core_params->dma_desc_fs_enable = 0;

			hsotg->params.dma_desc_enable = 0;

			hsotg->params.dma_desc_fs_enable = 0;

		}

	}
@@ -5249,7 +5249,7 @@ int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 
	hr = &hsotg->hr_backup;

	hr->hcfg = dwc2_readl(hsotg->regs + HCFG);

	hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);

	for (i = 0; i < hsotg->core_params->host_channels; ++i)

	for (i = 0; i < hsotg->params.host_channels; ++i)

		hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i));



	hr->hprt0 = dwc2_read_hprt0(hsotg);
@@ -5285,7 +5285,7 @@ int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 
	dwc2_writel(hr->hcfg, hsotg->regs + HCFG);

	dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK);



	for (i = 0; i < hsotg->core_params->host_channels; ++i)

	for (i = 0; i < hsotg->params.host_channels; ++i)

		dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i));



	dwc2_writel(hr->hprt0, hsotg->regs + HPRT0);