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Commit be8f4b15 authored by Suresh Vankadara's avatar Suresh Vankadara Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add CSI PHY and CCI nodes to sdmmagpie camera" into dev/msm-4.14-camx

parents bc198d10 6ee864c9

arch/arm64/boot/dts/qcom/sdmmagpie-camera.dtsi

+303 −0
Original line number Diff line number Diff line
@@ -17,6 +17,309 @@ 
		status = "ok";

	};



	cam_csiphy0: qcom,csiphy@ace0000 {

		cell-index = <0>;

		compatible = "qcom,csiphy-v1.2", "qcom,csiphy";

		reg = <0x0ace0000 0x2000>;

		reg-names = "csiphy";

		reg-cam-base = <0xe0000>;

		interrupts = <0 477 0>;

		interrupt-names = "csiphy";

		regulator-names = "gdscr", "refgen";

		gdscr-supply = <&titan_top_gdsc>;

		refgen-supply = <&refgen>;

		csi-vdd-voltage = <1200000>;

		mipi-csi-vdd-supply = <&pm6150l_l3>;

		clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,

			<&clock_camcc CAM_CC_CSIPHY0_CLK>,

			<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,

			<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>;

		clock-names = "cphy_rx_clk_src",

			"csiphy0_clk",

			"csi0phytimer_clk_src",

			"csi0phytimer_clk";

		src-clock-name = "csi0phytimer_clk_src";

		clock-cntl-level = "svs_l1", "turbo";

		clock-rates =

			<400000000 0 300000000 0>,

			<400000000 0 300000000 0>;

		status = "ok";

	};



	cam_csiphy1: qcom,csiphy@ace2000{

		cell-index = <1>;

		compatible = "qcom,csiphy-v1.2", "qcom,csiphy";

		reg = <0xace2000 0x2000>;

		reg-names = "csiphy";

		reg-cam-base = <0xe2000>;

		interrupts = <0 478 0>;

		interrupt-names = "csiphy";

		regulator-names = "gdscr", "refgen";

		gdscr-supply = <&titan_top_gdsc>;

		refgen-supply = <&refgen>;

		csi-vdd-voltage = <1200000>;

		mipi-csi-vdd-supply = <&pm6150l_l3>;

		clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,

			<&clock_camcc CAM_CC_CSIPHY1_CLK>,

			<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,

			<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>;

		clock-names = "cphy_rx_clk_src",

			"csiphy1_clk",

			"csi1phytimer_clk_src",

			"csi1phytimer_clk";

		src-clock-name = "csi1phytimer_clk_src";

		clock-cntl-level = "svs_l1", "turbo";

		clock-rates =

			<400000000 0 300000000 0>,

			<400000000 0 300000000 0>;



		status = "ok";

	};



	cam_csiphy2: qcom,csiphy@ace4000 {

		cell-index = <2>;

		compatible = "qcom,csiphy-v1.2", "qcom,csiphy";

		reg = <0xace4000 0x2000>;

		reg-names = "csiphy";

		reg-cam-base = <0xe4000>;

		interrupts = <0 479 0>;

		interrupt-names = "csiphy";

		regulator-names = "gdscr", "refgen";

		gdscr-supply = <&titan_top_gdsc>;

		refgen-supply = <&refgen>;

		csi-vdd-voltage = <1200000>;

		mipi-csi-vdd-supply = <&pm6150l_l3>;

		clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,

			<&clock_camcc CAM_CC_CSIPHY2_CLK>,

			<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,

			<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>;

		clock-names = "cphy_rx_clk_src",

			"csiphy2_clk",

			"csi2phytimer_clk_src",

			"csi2phytimer_clk";

		src-clock-name = "csi2phytimer_clk_src";

		clock-cntl-level = "svs_l1", "turbo";

		clock-rates =

			<400000000 0 300000000 0>,

			<400000000 0 300000000 0>;

		status = "ok";

	};



	cam_csiphy3: qcom,csiphy@ace6000 {

		cell-index = <3>;

		compatible = "qcom,csiphy-v1.2", "qcom,csiphy";

		reg = <0xace6000 0x2000>;

		reg-names = "csiphy";

		reg-cam-base = <0xe6000>;

		interrupts = <0 607 0>;

		interrupt-names = "csiphy";

		regulator-names = "gdscr", "refgen";

		gdscr-supply = <&titan_top_gdsc>;

		refgen-supply = <&refgen>;

		csi-vdd-voltage = <1200000>;

		mipi-csi-vdd-supply = <&pm6150l_l3>;

		clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,

			<&clock_camcc CAM_CC_CSIPHY2_CLK>,

			<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,

			<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>;

		clock-names = "cphy_rx_clk_src",

			"csiphy3_clk",

			"csi3phytimer_clk_src",

			"csi3phytimer_clk";

		src-clock-name = "csi3phytimer_clk_src";

		clock-cntl-level = "svs_l1", "turbo";

		clock-rates =

			<400000000 0 300000000 0>,

			<400000000 0 300000000 0>;

		status = "ok";

	};



	cam_cci0: qcom,cci@ac4a000 {

		cell-index = <0>;

		compatible = "qcom,cci";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0xac4a000 0x1000>;

		reg-names = "cci";

		reg-cam-base = <0x4a000>;

		interrupt-names = "cci";

		interrupts = <0 460 0>;

		status = "ok";

		gdscr-supply = <&titan_top_gdsc>;

		regulator-names = "gdscr";

		clocks = <&clock_camcc CAM_CC_CCI_0_CLK>,

			<&clock_camcc CAM_CC_CCI_0_CLK_SRC>;

		clock-names = "cci_0_clk",

			"cci_0_clk_src";

		src-clock-name = "cci_0_clk_src";

		clock-cntl-level = "lowsvs";

		clock-rates = <0 37500000>;

		pinctrl-names = "cam_default", "cam_suspend";

		pinctrl-0 = <&cci0_active &cci1_active>;

		pinctrl-1 = <&cci0_suspend &cci1_suspend>;

		gpios = <&tlmm 17 0>,

			<&tlmm 18 0>,

			<&tlmm 19 0>,

			<&tlmm 20 0>;

		gpio-req-tbl-num = <0 1 2 3>;

		gpio-req-tbl-flags = <1 1 1 1>;

		gpio-req-tbl-label = "CCI_I2C_DATA0",

					"CCI_I2C_CLK0",

					"CCI_I2C_DATA1",

					"CCI_I2C_CLK1";



		i2c_freq_100Khz_cci0: qcom,i2c_standard_mode {

			hw-thigh = <201>;

			hw-tlow = <174>;

			hw-tsu-sto = <204>;

			hw-tsu-sta = <231>;

			hw-thd-dat = <22>;

			hw-thd-sta = <162>;

			hw-tbuf = <227>;

			hw-scl-stretch-en = <0>;

			hw-trdhld = <6>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};



		i2c_freq_400Khz_cci0: qcom,i2c_fast_mode {

			hw-thigh = <38>;

			hw-tlow = <56>;

			hw-tsu-sto = <40>;

			hw-tsu-sta = <40>;

			hw-thd-dat = <22>;

			hw-thd-sta = <35>;

			hw-tbuf = <62>;

			hw-scl-stretch-en = <0>;

			hw-trdhld = <6>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};



		i2c_freq_custom_cci0: qcom,i2c_custom_mode {

			hw-thigh = <38>;

			hw-tlow = <56>;

			hw-tsu-sto = <40>;

			hw-tsu-sta = <40>;

			hw-thd-dat = <22>;

			hw-thd-sta = <35>;

			hw-tbuf = <62>;

			hw-scl-stretch-en = <1>;

			hw-trdhld = <6>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};



		i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode {

			hw-thigh = <16>;

			hw-tlow = <22>;

			hw-tsu-sto = <17>;

			hw-tsu-sta = <18>;

			hw-thd-dat = <16>;

			hw-thd-sta = <15>;

			hw-tbuf = <24>;

			hw-scl-stretch-en = <0>;

			hw-trdhld = <3>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};

	};



	cam_cci1: qcom,cci@ac4b000 {

		cell-index = <1>;

		compatible = "qcom,cci";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0xac4b000 0x1000>;

		reg-names = "cci";

		reg-cam-base = <0x4b000>;

		interrupt-names = "cci";

		interrupts = <0 461 0>;

		status = "ok";

		gdscr-supply = <&titan_top_gdsc>;

		regulator-names = "gdscr";

		clocks = <&clock_camcc CAM_CC_CCI_1_CLK>,

			<&clock_camcc CAM_CC_CCI_1_CLK_SRC>;

		clock-names = "cci_clk",

			"cci_1_clk_src";

		src-clock-name = "cci_1_clk_src";

		clock-cntl-level = "lowsvs";

		clock-rates = <0 37500000>;

		pinctrl-names = "cam_default", "cam_suspend";

		pinctrl-0 = <&cci2_active>;

		pinctrl-1 = <&cci2_suspend>;

		gpios = <&tlmm 27 0>,

			<&tlmm 28 0>;

		gpio-req-tbl-num = <0 1>;

		gpio-req-tbl-flags = <1 1>;

		gpio-req-tbl-label = "CCI_I2C_DATA2",

					"CCI_I2C_CLK2";



		i2c_freq_100Khz_cci1: qcom,i2c_standard_mode {

			hw-thigh = <201>;

			hw-tlow = <174>;

			hw-tsu-sto = <204>;

			hw-tsu-sta = <231>;

			hw-thd-dat = <22>;

			hw-thd-sta = <162>;

			hw-tbuf = <227>;

			hw-scl-stretch-en = <0>;

			hw-trdhld = <6>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};



		i2c_freq_400Khz_cci1: qcom,i2c_fast_mode {

			hw-thigh = <38>;

			hw-tlow = <56>;

			hw-tsu-sto = <40>;

			hw-tsu-sta = <40>;

			hw-thd-dat = <22>;

			hw-thd-sta = <35>;

			hw-tbuf = <62>;

			hw-scl-stretch-en = <0>;

			hw-trdhld = <6>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};



		i2c_freq_custom_cci1: qcom,i2c_custom_mode {

			hw-thigh = <38>;

			hw-tlow = <56>;

			hw-tsu-sto = <40>;

			hw-tsu-sta = <40>;

			hw-thd-dat = <22>;

			hw-thd-sta = <35>;

			hw-tbuf = <62>;

			hw-scl-stretch-en = <1>;

			hw-trdhld = <6>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};



		i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode {

			hw-thigh = <16>;

			hw-tlow = <22>;

			hw-tsu-sto = <17>;

			hw-tsu-sta = <18>;

			hw-thd-dat = <16>;

			hw-thd-sta = <15>;

			hw-tbuf = <24>;

			hw-scl-stretch-en = <0>;

			hw-trdhld = <3>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};

	};



	qcom,cam_smmu {

		compatible = "qcom,msm-cam-smmu";

		status = "ok";

arch/arm64/boot/dts/qcom/sdmmagpie-pinctrl.dtsi

+85 −0
Original line number Diff line number Diff line
@@ -866,6 +866,91 @@ 
				};

			};

		};



		cci0_active: cci0_active {

			mux {

				/* CLK, DATA */

				pins = "gpio17","gpio18"; // Only 2

				function = "cci_i2c";

			};



			config {

				pins = "gpio17","gpio18";

				bias-pull-up; /* PULL UP*/

				drive-strength = <2>; /* 2 MA */

			};

		};



		cci0_suspend: cci0_suspend {

			mux {

				/* CLK, DATA */

				pins = "gpio17","gpio18";

				function = "cci_i2c";

			};



			config {

				pins = "gpio17","gpio18";

				bias-pull-down; /* PULL DOWN */

				drive-strength = <2>; /* 2 MA */

			};

		};



		cci1_active: cci1_active {

			mux {

				/* CLK, DATA */

				pins = "gpio19","gpio20";

				function = "cci_i2c";

			};



			config {

				pins = "gpio19","gpio20";

				bias-pull-up; /* PULL UP*/

				drive-strength = <2>; /* 2 MA */

			};

		};



		cci1_suspend: cci1_suspend {

			mux {

				/* CLK, DATA */

				pins = "gpio19","gpio20";

				function = "cci_i2c";

			};



			config {

				pins = "gpio19","gpio20";

				bias-pull-down; /* PULL DOWN */

				drive-strength = <2>; /* 2 MA */

			};

		};



		cci2_active: cci2_active {

			mux {

				/* CLK, DATA */

				pins = "gpio27","gpio28";

				function = "cci_i2c";

			};



			config {

				pins = "gpio27","gpio28";

				bias-pull-up; /* PULL UP*/

				drive-strength = <2>; /* 2 MA */

			};

		};



		cci2_suspend: cci2_suspend {

			mux {

				/* CLK, DATA */

				pins = "gpio27","gpio28";

				function = "cci_i2c";

			};



			config {

				pins = "gpio27","gpio28";

				bias-pull-down; /* PULL DOWN */

				drive-strength = <2>; /* 2 MA */

			};

		};



		/* SDC pin type */

		sdc1_clk_on: sdc1_clk_on {

			config {

arch/arm64/boot/dts/qcom/sdmmagpie.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -2297,7 +2297,6 @@ 
#include "sdmmagpie-gdsc.dtsi"

#include "sdmmagpie-bus.dtsi"

#include "sdmmagpie-qupv3.dtsi"

#include "sdmmagpie-camera.dtsi"



&pcie_0_gdsc {

	status = "ok";
@@ -2418,6 +2417,7 @@ 
#include "pm6150l.dtsi"

#include "pm8009.dtsi"

#include "sdmmagpie-regulator.dtsi"

#include "sdmmagpie-camera.dtsi"

#include "sdmmagpie-coresight.dtsi"

#include "sdmmagpie-usb.dtsi"

#include "sdmmagpie-thermal.dtsi"