Commit be71b855 authored Feb 12, 2009 by Andi Kleen Committed by H. Peter Anvin Feb 24, 2009

x86, mce, cmci: recheck CMCI banks after APIC has been enabled on CPU #0



Impact: Fix marginal race condition

One the first CPU the machine checks are enabled early before
the local APIC is enabled. This could in theory lead
to some lost CMCI events very early during boot because
CMCIs cannot be delivered with disabled LAPIC.

The poller also doesn't recover from this because it doesn't
check CMCI banks.

Add an explicit CMCI banks check after the LAPIC is enabled.
This is only done for CPU #0, the other CPUs only initialize
machine checks after the LAPIC is on.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>

parent 5ca8681c

arch/x86/kernel/apic.c

+7 −0

Original line number	Diff line number	Diff line
		@@ -48,6 +48,7 @@
		#include <asm/apic.h>
		#include <asm/i8259.h>
		#include <asm/smp.h>
		#include <asm/mce.h>

		#include <mach_apic.h>
		#include <mach_apicdef.h>
		@@ -1270,6 +1271,12 @@ void __cpuinit setup_local_APIC(void)
		apic_write(APIC_LVT1, value);

		preempt_enable();

		#ifdef CONFIG_X86_MCE_INTEL
		/* Recheck CMCI information after local APIC is up on CPU #0 */
		if (smp_processor_id() == 0)
		cmci_recheck();
		#endif
		}

		void __cpuinit end_local_APIC_setup(void)