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Commit bd0a78cd authored by Govinda Rajulu Chenna's avatar Govinda Rajulu Chenna Committed by Gerrit - the friendly Code Review server
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drm/msm/dp: add widebus support for sst and mst modes 



Implement widebus support for all dp use-cases as per the
hardware design recommendations. Widebus reduces the dp
pclk by half and doubles the sw_m and sw_n values to correct
the stream configuration data.

CRs-Fixed: 2325207
Change-Id: Ieb2e4a21bc82ab73563a4fd2edb68e59dda29069
Signed-off-by: default avatarGovinda Rajulu Chenna <gchenna@codeaurora.org>
parent 38454009

drivers/gpu/drm/msm/dp/dp_catalog.c

+23 −1
Original line number Diff line number Diff line
@@ -935,6 +935,11 @@ static void dp_catalog_panel_config_msa(struct dp_catalog_panel *panel, 
		 * always be within the range of a 32 bit unsigned int.

		 */

		mvid = (u32) mvid_calc;



		if (panel->widebus_en) {

			mvid <<= 1;

			nvid <<= 1;

		}

	} else {

		io_data = catalog->io.dp_mmss_cc;
@@ -952,6 +957,9 @@ static void dp_catalog_panel_config_msa(struct dp_catalog_panel *panel, 


		pr_debug("rate = %d\n", rate);



		if (panel->widebus_en)

			mvid <<= 1;



		if (link_rate_hbr2 == rate)

			nvid *= 2;
@@ -1719,7 +1727,7 @@ static int dp_catalog_panel_timing_cfg(struct dp_catalog_panel *panel) 
{

	struct dp_catalog_private *catalog;

	struct dp_io_data *io_data;

	u32 offset = 0;

	u32 offset = 0, reg;



	if (!panel) {

		pr_err("invalid input\n");
@@ -1745,6 +1753,20 @@ static int dp_catalog_panel_timing_cfg(struct dp_catalog_panel *panel) 
		DP_HSYNC_VSYNC_WIDTH_POLARITY + offset, panel->width_blanking);

	dp_write(catalog->exe_mode, io_data, DP_ACTIVE_HOR_VER + offset,

			panel->dp_active);



	if (panel->stream_id == DP_STREAM_0)

		io_data = catalog->io.dp_p0;

	else

		io_data = catalog->io.dp_p1;



	reg = dp_read(catalog->exe_mode, io_data, MMSS_DP_INTF_CONFIG);



	if (panel->widebus_en)

		reg |= BIT(4);

	else

		reg &= ~BIT(4);



	dp_write(catalog->exe_mode, io_data, MMSS_DP_INTF_CONFIG, reg);

end:

	return 0;

}

drivers/gpu/drm/msm/dp/dp_catalog.h

+2 −0
Original line number Diff line number Diff line
@@ -197,6 +197,8 @@ struct dp_catalog_panel { 


	enum dp_stream_id stream_id;



	bool widebus_en;



	int (*timing_cfg)(struct dp_catalog_panel *panel);

	void (*config_hdr)(struct dp_catalog_panel *panel, bool en);

	void (*tpg_config)(struct dp_catalog_panel *panel, bool enable);

drivers/gpu/drm/msm/dp/dp_catalog_v200.c

+8 −0
Original line number Diff line number Diff line
@@ -171,6 +171,11 @@ static void dp_catalog_panel_config_msa_v200(struct dp_catalog_panel *panel, 
		 * always be within the range of a 32 bit unsigned int.

		 */

		mvid = (u32) mvid_calc;



		if (panel->widebus_en) {

			mvid <<= 1;

			nvid <<= 1;

		}

	} else {

		io_data = catalog->io->dp_mmss_cc;
@@ -189,6 +194,9 @@ static void dp_catalog_panel_config_msa_v200(struct dp_catalog_panel *panel, 


		pr_debug("rate = %d\n", rate);



		if (panel->widebus_en)

			mvid <<= 1;



		if (link_rate_hbr2 == rate)

			nvid *= 2;

drivers/gpu/drm/msm/dp/dp_catalog_v420.c

+8 −0
Original line number Diff line number Diff line
@@ -145,6 +145,11 @@ static void dp_catalog_panel_config_msa_v420(struct dp_catalog_panel *panel, 
		 * always be within the range of a 32 bit unsigned int.

		 */

		mvid = (u32) mvid_calc;



		if (panel->widebus_en) {

			mvid <<= 1;

			nvid <<= 1;

		}

	} else {

		io_data = catalog->io->dp_mmss_cc;
@@ -162,6 +167,9 @@ static void dp_catalog_panel_config_msa_v420(struct dp_catalog_panel *panel, 


		pr_debug("rate = %d\n", rate);



		if (panel->widebus_en)

			mvid <<= 1;



		if (link_rate_hbr2 == rate)

			nvid *= 2;

drivers/gpu/drm/msm/dp/dp_ctrl.c

+20 −16
Original line number Diff line number Diff line
@@ -615,6 +615,9 @@ static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl, 
		struct dp_panel *dp_panel)

{

	int ret = 0;

	u32 pclk;

	enum dp_pm_type clk_type;

	char clk_name[32] = "";



	ret = ctrl->power->set_pixel_clk_parent(ctrl->power,

			dp_panel->stream_id);
@@ -623,26 +626,27 @@ static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl, 
		return ret;



	if (dp_panel->stream_id == DP_STREAM_0) {

		dp_ctrl_set_clock_rate(ctrl, "strm0_pixel_clk", DP_STREAM0_PM,

				dp_panel->pinfo.pixel_clk_khz);



		ret = ctrl->power->clk_enable(ctrl->power, DP_STREAM0_PM, true);

		if (ret) {

			pr_err("Unabled to start stream0 clocks\n");

			ret = -EINVAL;

		}

		clk_type = DP_STREAM0_PM;

		strlcpy(clk_name, "strm0_pixel_clk", 32);

	} else if (dp_panel->stream_id == DP_STREAM_1) {

		dp_ctrl_set_clock_rate(ctrl, "strm1_pixel_clk", DP_STREAM1_PM,

				dp_panel->pinfo.pixel_clk_khz);



		ret = ctrl->power->clk_enable(ctrl->power, DP_STREAM1_PM, true);

		if (ret) {

			pr_err("Unabled to start stream1 clocks\n");

			ret = -EINVAL;

		}

		clk_type = DP_STREAM1_PM;

		strlcpy(clk_name, "strm1_pixel_clk", 32);

	} else {

		pr_err("Invalid stream:%d for clk enable\n",

				dp_panel->stream_id);

		return -EINVAL;

	}



	pclk = dp_panel->pinfo.widebus_en ?

		(dp_panel->pinfo.pixel_clk_khz >> 1) :

		(dp_panel->pinfo.pixel_clk_khz);



	dp_ctrl_set_clock_rate(ctrl, clk_name, clk_type, pclk);



	ret = ctrl->power->clk_enable(ctrl->power, clk_type, true);

	if (ret) {

		pr_err("Unabled to start stream:%d clocks\n",

				dp_panel->stream_id);

		ret = -EINVAL;

	}