Loading drivers/clk/qcom/gcc-sm8150.c +2 −2 Original line number Diff line number Diff line Loading @@ -2276,7 +2276,7 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = { static struct clk_branch gcc_pcie_0_pipe_clk = { .halt_reg = 0x6b024, .halt_check = BRANCH_VOTED, .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(4), Loading Loading @@ -2376,7 +2376,7 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = { static struct clk_branch gcc_pcie_1_pipe_clk = { .halt_reg = 0x8d024, .halt_check = BRANCH_VOTED, .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(30), Loading Loading
drivers/clk/qcom/gcc-sm8150.c +2 −2 Original line number Diff line number Diff line Loading @@ -2276,7 +2276,7 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = { static struct clk_branch gcc_pcie_0_pipe_clk = { .halt_reg = 0x6b024, .halt_check = BRANCH_VOTED, .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(4), Loading Loading @@ -2376,7 +2376,7 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = { static struct clk_branch gcc_pcie_1_pipe_clk = { .halt_reg = 0x8d024, .halt_check = BRANCH_VOTED, .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(30), Loading