Merge branch 'perf' into devel (bc85e585) · Commits · e / devices / android_kernel_oneplus_sm8150

arch/arm/Kconfig

+15 −0

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		@@ -20,6 +20,8 @@ config ARM
		select HAVE_GENERIC_DMA_COHERENT
		select HAVE_KERNEL_GZIP
		select HAVE_KERNEL_LZO
		select HAVE_PERF_EVENTS
		select PERF_USE_VMALLOC
		help
		The ARM series is a line of low-power-consumption RISC chip designs
		licensed by ARM Ltd and targeted at embedded applications and
		@@ -877,6 +879,11 @@ config XSCALE_PMU
		depends on CPU_XSCALE && !XSCALE_PMU_TIMER
		default y

		config CPU_HAS_PMU
		depends on CPU_V6 \|\| CPU_V7 \|\| XSCALE_PMU
		default y
		bool

		if !MMU
		source "arch/arm/Kconfig-nommu"
		endif
		@@ -1181,6 +1188,14 @@ config HIGHPTE
		depends on HIGHMEM
		depends on !OUTER_CACHE

		config HW_PERF_EVENTS
		bool "Enable hardware performance counter support for perf events"
		depends on PERF_EVENTS && CPU_HAS_PMU && (CPU_V6 \|\| CPU_V7)
		default y
		help
		Enable hardware performance counter support for perf events. If
		disabled, perf events will use software events only.

		source "mm/Kconfig"

		config LEDS

arch/arm/include/asm/perf_event.h

0 → 100644

+31 −0

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		/*
		* linux/arch/arm/include/asm/perf_event.h
		*
		* Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*
		*/

		#ifndef __ARM_PERF_EVENT_H__
		#define __ARM_PERF_EVENT_H__

		/*
		* NOP: on most (read: all supported) ARM platforms, the performance
		* counter interrupts are regular interrupts and not an NMI. This
		* means that when we receive the interrupt we can call
		* perf_event_do_pending() that handles all of the work with
		* interrupts enabled.
		*/
		static inline void
		set_perf_event_pending(void)
		{
		}

		/* ARM performance counters start from 1 (in the cp15 accesses) so use the
		* same indexes here for consistency. */
		#define PERF_EVENT_INDEX_OFFSET 1

		#endif /* __ARM_PERF_EVENT_H__ */

arch/arm/include/asm/pmu.h

0 → 100644

+75 −0

Original line number	Diff line number	Diff line
		/*
		* linux/arch/arm/include/asm/pmu.h
		*
		* Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*
		*/

		#ifndef __ARM_PMU_H__
		#define __ARM_PMU_H__

		#ifdef CONFIG_CPU_HAS_PMU

		struct pmu_irqs {
		const int *irqs;
		int num_irqs;
		};

		/**
		* reserve_pmu() - reserve the hardware performance counters
		*
		* Reserve the hardware performance counters in the system for exclusive use.
		* The 'struct pmu_irqs' for the system is returned on success, ERR_PTR()
		* encoded error on failure.
		*/
		extern const struct pmu_irqs *
		reserve_pmu(void);

		/**
		* release_pmu() - Relinquish control of the performance counters
		*
		* Release the performance counters and allow someone else to use them.
		* Callers must have disabled the counters and released IRQs before calling
		* this. The 'struct pmu_irqs' returned from reserve_pmu() must be passed as
		* a cookie.
		*/
		extern int
		release_pmu(const struct pmu_irqs *irqs);

		/**
		* init_pmu() - Initialise the PMU.
		*
		* Initialise the system ready for PMU enabling. This should typically set the
		* IRQ affinity and nothing else. The users (oprofile/perf events etc) will do
		* the actual hardware initialisation.
		*/
		extern int
		init_pmu(void);

		#else /* CONFIG_CPU_HAS_PMU */

		static inline const struct pmu_irqs *
		reserve_pmu(void)
		{
		return ERR_PTR(-ENODEV);
		}

		static inline int
		release_pmu(const struct pmu_irqs *irqs)
		{
		return -ENODEV;
		}

		static inline int
		init_pmu(void)
		{
		return -ENODEV;
		}

		#endif /* CONFIG_CPU_HAS_PMU */

		#endif /* __ARM_PMU_H__ */

arch/arm/kernel/Makefile

+2 −0

Original line number	Diff line number	Diff line
		@@ -46,6 +46,8 @@ obj-$(CONFIG_CPU_XSCALE) += xscale-cp0.o
		obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o
		obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o
		obj-$(CONFIG_IWMMXT) += iwmmxt.o
		obj-$(CONFIG_CPU_HAS_PMU) += pmu.o
		obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o
		AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt

		ifneq ($(CONFIG_ARCH_EBSA110),y)