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Commit bc554045 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Enable cpu node on SDXPRAIRIE"

parents a5fabc98 2145e2cb

arch/arm64/boot/dts/qcom/sdxprairie.dtsi

+5 −4
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 


#include "skeleton.dtsi"

#include <dt-bindings/clock/qcom,gcc-sdxprairie.h>

#include <dt-bindings/clock/qcom,cpu-sdxprairie.h>

#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/clock/qcom,aop-qmp.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -288,8 +289,9 @@ 


	clock_cpu: qcom,clock-cpu@17808100 {

		compatible = "qcom,cpu-sdxprairie";

		clocks = <&clock_rpmh RPMH_CXO_CLK>;

		clock-names = "bi_tcxo";

		clocks = <&clock_rpmh RPMH_CXO_CLK>,

			 <&clock_gcc GPLL0>;

		clock-names = "bi_tcxo", "gpll0";

		reg = <0x17810008 0x8>,

			<0x17808100 0x44>;

		reg-names = "apcs_cmd" , "apcs_pll";
@@ -300,9 +302,8 @@ 
			<  345600000 RPMH_REGULATOR_LEVEL_LOW_SVS>,

			<  576000000 RPMH_REGULATOR_LEVEL_SVS>,

			< 1094400000 RPMH_REGULATOR_LEVEL_NOM>,

			< 1555200000 RPMH_REGULATOR_LEVEL_TURBO>;

			< 1497600000 RPMH_REGULATOR_LEVEL_TURBO>;

		#clock-cells = <1>;

		status = "disabled";

	};



	spmi_bus: qcom,spmi@c440000 {

drivers/clk/qcom/clk-alpha-pll.c

+39 −2
Original line number Diff line number Diff line
@@ -2322,6 +2322,33 @@ const struct clk_ops clk_agera_pll_ops = { 
};

EXPORT_SYMBOL(clk_agera_pll_ops);



static void clk_alpha_pll_lucid_list_registers(struct seq_file *f,

							struct clk_hw *hw)

{

	static struct clk_register_data pll_regs[] = {

		{"PLL_MODE", 0x0},

		{"PLL_L_VAL", 0x4},

		{"PLL_CAL_L_VAL", 0x8},

		{"PLL_USER_CTL", 0x0c},

		{"PLL_USER_CTL_U", 0x10},

		{"PLL_USER_CTL_U1", 0x14},

		{"PLL_CONFIG_CTL", 0x18},

		{"PLL_CONFIG_CTL_U", 0x1c},

		{"PLL_CONFIG_CTL_U1", 0x20},

		{"PLL_TEST_CTL", 0x24},

		{"PLL_TEST_CTL_U", 0x28},

		{"PLL_STATUS", 0x30},

		{"PLL_ALPHA_VAL", 0x40},

	};



	static struct clk_register_data pll_vote_reg = {

		"APSS_PLL_VOTE", 0x0

	};



	print_pll_registers(f, hw, pll_regs, ARRAY_SIZE(pll_regs),

							&pll_vote_reg);

}



static int lucid_pll_is_enabled(struct clk_alpha_pll *pll,

					struct regmap *regmap)

{
@@ -2493,6 +2520,9 @@ static int alpha_pll_lucid_prepare(struct clk_hw *hw) 
	unsigned long prate;

	int ret;



	if (pll->flags & SUPPORTS_NO_SLEW)

		return 0;



	/* Return early if calibration is not needed. */

	ret = regmap_read(pll->clkr.regmap, pll->offset + LUCID_PLL_OFF_STATUS,

		      &regval);
@@ -2522,7 +2552,7 @@ static unsigned long 
alpha_pll_lucid_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	u32 l, frac;

	u32 l = 0, frac = 0;



	regmap_read(pll->clkr.regmap, pll->offset + LUCID_PLL_OFF_L_VAL, &l);

	regmap_read(pll->clkr.regmap, pll->offset + LUCID_PLL_OFF_ALPHA_VAL,
@@ -2551,10 +2581,16 @@ static int alpha_pll_lucid_set_rate(struct clk_hw *hw, unsigned long rate, 
		return -EINVAL;

	}



	if (pll->flags & SUPPORTS_NO_SLEW)

		alpha_pll_lucid_disable(hw);



	regmap_write(pll->clkr.regmap, pll->offset + LUCID_PLL_OFF_L_VAL, l);

	regmap_write(pll->clkr.regmap, pll->offset + LUCID_PLL_OFF_ALPHA_VAL,

							a);



	if (pll->flags & SUPPORTS_NO_SLEW)

		return alpha_pll_lucid_enable(hw);



	/* Latch the PLL input */

	ret = regmap_update_bits(pll->clkr.regmap, pll->offset + PLL_MODE,

			   LUCID_PLL_UPDATE, LUCID_PLL_UPDATE);
@@ -2601,7 +2637,7 @@ const struct clk_ops clk_alpha_pll_lucid_ops = { 
	.recalc_rate = alpha_pll_lucid_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = alpha_pll_lucid_set_rate,

	.list_registers = clk_alpha_pll_list_registers,

	.list_registers = clk_alpha_pll_lucid_list_registers,

};

EXPORT_SYMBOL(clk_alpha_pll_lucid_ops);
@@ -2611,6 +2647,7 @@ const struct clk_ops clk_alpha_pll_fixed_lucid_ops = { 
	.is_enabled = alpha_pll_lucid_is_enabled,

	.recalc_rate = alpha_pll_lucid_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.list_registers = clk_alpha_pll_lucid_list_registers,

};

EXPORT_SYMBOL(clk_alpha_pll_fixed_lucid_ops);

drivers/clk/qcom/clk-alpha-pll.h

+1 −0
Original line number Diff line number Diff line
@@ -76,6 +76,7 @@ struct clk_alpha_pll { 
#define SUPPORTS_SLEW		BIT(4)

	/* Associated with soft_vote for multiple PLL software instances */

#define SUPPORTS_FSM_VOTE	BIT(5)

#define SUPPORTS_NO_SLEW	BIT(6)

	u8 flags;



	struct clk_regmap clkr;

drivers/clk/qcom/clk-cpu-sdxprairie.c

+50 −5
Original line number Diff line number Diff line
@@ -30,9 +30,10 @@ 
#define to_clk_regmap_mux_div(_hw) \

	container_of(to_clk_regmap(_hw), struct clk_regmap_mux_div, clkr)



#define REG_OFFSET	0x4

#define APCS_PLL	0x17808100

#define APCS_CMD	0x17810008

#define REG_OFFSET	0x4



#define XO_RATE		19200000



/* PLL speficic settings and offsets */
@@ -185,6 +186,27 @@ static u8 cpucc_clk_get_parent(struct clk_hw *hw) 
	return clk_regmap_mux_div_ops.get_parent(hw);

}



/*

 * We use the notifier function for switching to a temporary safe configuration

 * (mux and divider), while the APSS pll is reconfigured.

 */

static int cpucc_notifier_cb(struct notifier_block *nb, unsigned long event,

			     void *data)

{

	struct clk_regmap_mux_div *cpuclk = container_of(nb,

					struct clk_regmap_mux_div, clk_nb);

	int ret = 0;



	if (event == PRE_RATE_CHANGE)

		/* set the mux to safe source(gpll0) & div */

		ret = __mux_div_set_src_div(cpuclk,  cpuclk->safe_src, 1);



	if (event == ABORT_RATE_CHANGE)

		pr_err("Error in configuring PLL - stay at safe src only\n");



	return notifier_from_errno(ret);

}



static const struct clk_ops cpucc_clk_ops = {

	.enable = cpucc_clk_enable,

	.disable = cpucc_clk_disable,
@@ -219,6 +241,7 @@ static struct clk_alpha_pll apcs_cpu_pll = { 
	.type = LUCID_PLL,

	.vco_table = lucid_vco,

	.num_vco = ARRAY_SIZE(lucid_vco),

	.flags = SUPPORTS_NO_SLEW,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "apcs_cpu_pll",

		.parent_names = (const char *[]){ "bi_tcxo_ao" },
@@ -240,7 +263,10 @@ static struct clk_regmap_mux_div apcs_mux_clk = { 
	.hid_shift  = 0,

	.src_width  = 3,

	.src_shift  = 8,

	.safe_src = 1,

	.safe_div = 1,

	.parent_map = apcs_mux_clk_parent_map,

	.clk_nb.notifier_call = cpucc_notifier_cb,

	.clkr.hw.init = &(struct clk_init_data) {

		.name = "apcs_mux_clk",

		.parent_names = apcs_mux_clk_parent_name,
@@ -482,6 +508,13 @@ static int cpucc_driver_probe(struct platform_device *pdev) 
		return PTR_ERR(clk);

	}



	clk = devm_clk_get(dev, "gpll0");

	if (IS_ERR(clk)) {

		if (PTR_ERR(clk) != -EPROBE_DEFER)

			dev_err(dev, "Unable to get GPLL0 clock\n");

		return PTR_ERR(clk);

	}



	 /* Rail Regulator for apcs_cpu_pll & cpuss mux*/

	vdd_lucid_pll.regulator[0] = devm_regulator_get(&pdev->dev,

							"vdd-lucid-pll");
@@ -554,7 +587,7 @@ static int cpucc_driver_probe(struct platform_device *pdev) 


	ret = of_property_read_u32(of, "qcom,cpucc-init-rate", &rate);

	if (ret || !rate)

		dev_err(&pdev->dev, "Init rate for clock not defined\n");

		dev_dbg(&pdev->dev, "Init rate for clock not defined\n");



	cpucc_clk_init_rate = max(cpucc_clk_init_rate, rate);
@@ -580,6 +613,13 @@ static int cpucc_driver_probe(struct platform_device *pdev) 
		return ret;

	}



	ret = clk_notifier_register(apcs_mux_clk.clkr.hw.clk,

							&apcs_mux_clk.clk_nb);

	if (ret) {

		dev_err(dev, "failed to register clock notifier: %d\n", ret);

		return ret;

	}



	/* Set to boot frequency */

	ret = clk_set_rate(apcs_mux_clk.clkr.hw.clk, cpucc_clk_init_rate);

	if (ret)
@@ -599,6 +639,7 @@ static int cpucc_driver_probe(struct platform_device *pdev) 
	put_online_cpus();



	cpucc_clk_populate_opp_table(pdev);



	dev_info(dev, "CPU clock Driver probed successfully\n");



	return ret;
@@ -654,7 +695,9 @@ static void __init configure_lucid_pll(void __iomem *base) 
	u32 regval;



	/* Starting the PLL is in the OFF mode */

	writel_relaxed(0x0, base + apcs_cpu_pll.offset);

	regval = readl_relaxed(base);

	regval |= BIT(0);

	writel_relaxed(regval, base);



	/* Program the PLL’s user, config, and test registers */

	writel_relaxed(0x1, base + LUCID_PLL_OFF_USER_CTL);
@@ -666,6 +709,7 @@ static void __init configure_lucid_pll(void __iomem *base) 


	/* Program the PLL L register and its associated calibration register */

	writel_relaxed(apcs_cpu_pll_config.l, base + LUCID_PLL_OFF_L_VAL);



	writel_relaxed(0x44, base + LUCID_PLL_OFF_CAL_L_VAL);



	/* Turn off the outputs */
@@ -686,8 +730,9 @@ static int __init cpu_clock_init(void) 
{

	struct device_node *dev;

	void __iomem  *base;

	int count, regval = 0, l_val;

	int count, l_val;

	unsigned long enable_mask = 0x7;

	u32 regval;



	dev = of_find_compatible_node(NULL, NULL, "qcom,cpu-sdxprairie");

	if (!dev) {