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Commit bc4539d5 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "power: smb5: Evaluate step charging on wdog snarl"

parents 5c0468ef e5084ae5

Documentation/devicetree/bindings/power/supply/qcom/qpnp-smb5.txt

+8 −0
Original line number Diff line number Diff line
@@ -313,6 +313,14 @@ Charger specific properties: 
		connector THERM, only valid values are (0/30/100/400).

		If not specified 100K is used as default pull-up.



- qcom,wd-snarl-time-config

  Usage:      optional

  Value type: <u32>

  Definition: WDOG snarl timeout configuration value. The possible values are

		0 to 7, where 0 = 62.5ms, 1 = 125ms, 2 = 250ms, 3 = 500ms,

		4 = 1s, 5 = 2s, 6 = 4s and 7 = 8s. If not defined, wdog-snarl

		irq is disabled by default.



=============================================

Second Level Nodes - SMB5 Charger Peripherals

=============================================

drivers/power/supply/qcom/qpnp-smb5.c

+21 −6
Original line number Diff line number Diff line
@@ -217,6 +217,7 @@ struct smb_dt_props { 
	int			auto_recharge_soc;

	int			auto_recharge_vbat_mv;

	int			wd_bark_time;

	int			wd_snarl_time_cfg;

	int			batt_profile_fcc_ua;

	int			batt_profile_fv_uv;

	int			term_current_src;
@@ -417,6 +418,11 @@ static int smb5_parse_dt(struct smb5 *chip) 
	if (rc < 0 || chip->dt.wd_bark_time < MIN_WD_BARK_TIME)

		chip->dt.wd_bark_time = DEFAULT_WD_BARK_TIME;



	rc = of_property_read_u32(node, "qcom,wd-snarl-time-config",

					&chip->dt.wd_snarl_time_cfg);

	if (rc < 0)

		chip->dt.wd_snarl_time_cfg = -EINVAL;



	chip->dt.no_battery = of_property_read_bool(node,

						"qcom,batteryless-platform");
@@ -2280,9 +2286,17 @@ static int smb5_init_hw(struct smb5 *chip) 
	val = (ilog2(chip->dt.wd_bark_time / 16) << BARK_WDOG_TIMEOUT_SHIFT)

			& BARK_WDOG_TIMEOUT_MASK;

	val |= BITE_WDOG_TIMEOUT_8S;



	if (chip->dt.wd_snarl_time_cfg == -EINVAL)

		val |= SNARL_WDOG_TMOUT_8S;

	else

		val |= (chip->dt.wd_snarl_time_cfg << SNARL_WDOG_TIMEOUT_SHIFT)

			& SNARL_WDOG_TIMEOUT_MASK;



	rc = smblib_masked_write(chg, SNARL_BARK_BITE_WD_CFG_REG,

			BITE_WDOG_DISABLE_CHARGING_CFG_BIT |

			BARK_WDOG_TIMEOUT_MASK | BITE_WDOG_TIMEOUT_MASK,

			SNARL_WDOG_TIMEOUT_MASK | BARK_WDOG_TIMEOUT_MASK |

			BITE_WDOG_TIMEOUT_MASK,

			val);

	if (rc < 0) {

		pr_err("Couldn't configue WD config rc=%d\n", rc);
@@ -2875,13 +2889,14 @@ static int smb5_request_interrupts(struct smb5 *chip) 
		chg->usb_icl_change_irq_enabled = true;



	/*

	 * WDOG_SNARL_IRQ is required for SW Thermal Regulation WA only. In

	 * case the WA is not required, disable the WDOG_SNARL_IRQ to prevent

	 * interrupt storm.

	 * WDOG_SNARL_IRQ is required for SW Thermal Regulation WA. In case

	 * the WA is not required and neither is the snarl timer configuration

	 * defined, disable the WDOG_SNARL_IRQ to prevent interrupt storm.

	 */



	if (chg->irq_info[WDOG_SNARL_IRQ].irq && !(chg->wa_flags &

						SW_THERM_REGULATION_WA)) {

	if (chg->irq_info[WDOG_SNARL_IRQ].irq && (!(chg->wa_flags &

				SW_THERM_REGULATION_WA) &&

				chip->dt.wd_snarl_time_cfg == -EINVAL)) {

		disable_irq_wake(chg->irq_info[WDOG_SNARL_IRQ].irq);

		disable_irq_nosync(chg->irq_info[WDOG_SNARL_IRQ].irq);

	}

drivers/power/supply/qcom/smb5-lib.c

+3 −0
Original line number Diff line number Diff line
@@ -5491,6 +5491,9 @@ irqreturn_t wdog_snarl_irq_handler(int irq, void *data) 
		schedule_delayed_work(&chg->thermal_regulation_work, 0);

	}



	if (chg->step_chg_enabled)

		power_supply_changed(chg->batt_psy);



	return IRQ_HANDLED;

}

drivers/power/supply/qcom/smb5-reg.h

+1 −0
Original line number Diff line number Diff line
@@ -491,6 +491,7 @@ enum { 
#define SNARL_BARK_BITE_WD_CFG_REG		(MISC_BASE + 0x53)

#define BITE_WDOG_DISABLE_CHARGING_CFG_BIT	BIT(7)

#define SNARL_WDOG_TIMEOUT_MASK                 GENMASK(6, 4)

#define SNARL_WDOG_TIMEOUT_SHIFT		4

#define SNARL_WDOG_TMOUT_62P5MS			0x00

#define SNARL_WDOG_TMOUT_1S			0x40

#define SNARL_WDOG_TMOUT_8S			0x70