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Commit bc1c91eb authored by Damien Lespiau's avatar Damien Lespiau Committed by Daniel Vetter
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drm/i915: Fix primary plane offset on HSW 



Haswell consolidates DSP_TILEOFF and DSP_LINOFF into DSP_OFFSET (aka
PRI_OFFSET).

Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 94c6419e

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -3034,6 +3034,7 @@ 
#define _DSPASIZE		0x70190

#define _DSPASURF		0x7019C /* 965+ only */

#define _DSPATILEOFF		0x701A4 /* 965+ only */

#define _DSPAOFFSET		0x701A4 /* HSW */



#define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)

#define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
@@ -3043,6 +3044,7 @@ 
#define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)

#define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)

#define DSPLINOFF(plane) DSPADDR(plane)

#define DSPOFFSET(plane) _PIPE(plane, _DSPAOFFSET, _DSPBOFFSET)



/* Display/Sprite base address macros */

#define DISP_BASEADDR_MASK	(0xfffff000)
@@ -3088,6 +3090,7 @@ 
#define _DSPBSIZE		0x71190

#define _DSPBSURF		0x7119C

#define _DSPBTILEOFF		0x711A4

#define _DSPBOFFSET		0x711A4



/* Sprite A control */

#define _DVSACNTR		0x72180

drivers/gpu/drm/i915/intel_display.c

+6 −2
Original line number Diff line number Diff line
@@ -2128,8 +2128,12 @@ static int ironlake_update_plane(struct drm_crtc *crtc, 
	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);

	I915_MODIFY_DISPBASE(DSPSURF(plane),

			     obj->gtt_offset + intel_crtc->dspaddr_offset);

	if (IS_HASWELL(dev)) {

		I915_WRITE(DSPOFFSET(plane), (y << 16) | x);

	} else {

		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);

		I915_WRITE(DSPLINOFF(plane), linear_offset);

	}

	POSTING_READ(reg);



	return 0;