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Commit bb702612 authored by Subbaraman Narayanamurthy's avatar Subbaraman Narayanamurthy
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power: qpnp-fg-gen4: Allow delta MSOC/BSOC threshold configuration for 0.5% 



Currently, delta MSOC/BSOC threshold can be configured from 1 to
12 %. However, it can be configured in 0.5 % increments. This is
useful when SOC (State of Charge) required to be monitored more
accurately. Allow this configuration by changing the parameter to
be specified in deci-percentage unit (e.g. 10 is 1 %).

While at it, print the raw value of MSOC when delta MSOC
interrupt fires.

Change-Id: Ibd4c7fbd3452d503cf5fde0a29024d35b350b747
Signed-off-by: default avatarSubbaraman Narayanamurthy <subbaram@codeaurora.org>
parent ee9b982a

Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen4.txt

+3 −2
Original line number Diff line number Diff line
@@ -72,8 +72,9 @@ First Level Node - FG Gen4 device 
	Value type: <u32>

	Definition: Percentage of SOC increase upon which the delta monotonic &

		    battery SOC interrupts will be triggered. If this property

		    is not specified, then the default value will be 1.

		    Possible values are in the range of 0 to 12.

		    is not specified, then the default value will be 5 (0.5 %).

		    Unit is in deci-percentage. Possible values are in the range

		    of 1 to 124.



- qcom,fg-esr-timer-chg-fast

	Usage:      optional

drivers/power/supply/qcom/qpnp-fg-gen4.c

+11 −8
Original line number Diff line number Diff line
@@ -325,9 +325,9 @@ static struct fg_sram_param pm8150b_v1_sram_params[] = { 
	PARAM(SYS_TERM_CURR, SYS_TERM_CURR_WORD, SYS_TERM_CURR_OFFSET, 2,

		100000, 48828, 0, fg_encode_current, NULL),

	PARAM(DELTA_MSOC_THR, DELTA_MSOC_THR_WORD, DELTA_MSOC_THR_OFFSET,

		1, 2048, 100, 0, fg_encode_default, NULL),

		1, 2048, 1000, 0, fg_encode_default, NULL),

	PARAM(DELTA_BSOC_THR, DELTA_BSOC_THR_WORD, DELTA_BSOC_THR_OFFSET,

		1, 2048, 100, 0, fg_encode_default, NULL),

		1, 2048, 1000, 0, fg_encode_default, NULL),

	PARAM(ESR_TIMER_DISCHG_MAX, ESR_TIMER_DISCHG_MAX_WORD,

		ESR_TIMER_DISCHG_MAX_OFFSET, 1, 1, 1, 0, fg_encode_default,

		NULL),
@@ -417,9 +417,9 @@ static struct fg_sram_param pm8150b_v2_sram_params[] = { 
	PARAM(SYS_TERM_CURR, SYS_TERM_CURR_WORD, SYS_TERM_CURR_OFFSET, 2,

		100000, 48828, 0, fg_encode_current, NULL),

	PARAM(DELTA_MSOC_THR, DELTA_MSOC_THR_WORD, DELTA_MSOC_THR_OFFSET,

		1, 2048, 100, 0, fg_encode_default, NULL),

		1, 2048, 1000, 0, fg_encode_default, NULL),

	PARAM(DELTA_BSOC_THR, DELTA_BSOC_THR_WORD, DELTA_BSOC_THR_OFFSET,

		1, 2048, 100, 0, fg_encode_default, NULL),

		1, 2048, 1000, 0, fg_encode_default, NULL),

	PARAM(ESR_TIMER_DISCHG_MAX, ESR_TIMER_DISCHG_MAX_WORD,

		ESR_TIMER_DISCHG_MAX_OFFSET, 1, 1, 1, 0, fg_encode_default,

		NULL),
@@ -2728,10 +2728,13 @@ static irqreturn_t fg_delta_msoc_irq_handler(int irq, void *data) 
{

	struct fg_dev *fg = data;

	struct fg_gen4_chip *chip = container_of(fg, struct fg_gen4_chip, fg);

	int rc, batt_soc, batt_temp;

	int rc, batt_soc, batt_temp, msoc_raw;

	bool input_present = is_input_present(fg);



	fg_dbg(fg, FG_IRQ, "irq %d triggered\n", irq);

	rc = fg_get_msoc_raw(fg, &msoc_raw);

	if (!rc)

		fg_dbg(fg, FG_IRQ, "irq %d triggered msoc_raw: %d\n", irq,

			msoc_raw);



	get_batt_psy_props(fg);
@@ -3918,7 +3921,7 @@ static int fg_gen4_hw_init(struct fg_gen4_chip *chip) 
		}

	}



	if (chip->dt.delta_soc_thr > 0 && chip->dt.delta_soc_thr < 100) {

	if (chip->dt.delta_soc_thr > 0 && chip->dt.delta_soc_thr < 125) {

		fg_encode(fg->sp, FG_SRAM_DELTA_MSOC_THR,

			chip->dt.delta_soc_thr, buf);

		rc = fg_sram_write(fg,
@@ -4355,7 +4358,7 @@ static int fg_parse_esr_cal_params(struct fg_dev *fg) 
#define DEFAULT_EMPTY_VOLT_MV		2812

#define DEFAULT_SYS_TERM_CURR_MA	-125

#define DEFAULT_CUTOFF_CURR_MA		200

#define DEFAULT_DELTA_SOC_THR		1

#define DEFAULT_DELTA_SOC_THR		5	/* 0.5 % */

#define DEFAULT_CL_START_SOC		15

#define DEFAULT_CL_MIN_TEMP_DECIDEGC	150

#define DEFAULT_CL_MAX_TEMP_DECIDEGC	500