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Commit bb53a48f authored by Deepak Katragadda's avatar Deepak Katragadda
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ARM: dts: msm: Add GDSC support on SDMSHRIKE



Add the missing GDSC structures from SDM855 and enable all of
them for use on SDMSHRIKE.

Change-Id: I97b92e638eca7e9e0cea574cf99560040717d89a
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 49a6d871
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+60 −0
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/*
 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include "sdm855-gdsc.dtsi"

&soc {
	/* GDSCs in Global CC */
	pcie_2_gdsc: qcom,gdsc@19d004 {
		compatible = "qcom,gdsc";
		regulator-name = "pcie_2_gdsc";
		reg = <0x19d004 0x4>;
		status = "disabled";
	};

	pcie_3_gdsc: qcom,gdsc@1a3004 {
		compatible = "qcom,gdsc";
		regulator-name = "pcie_3_gdsc";
		reg = <0x1a3004 0x4>;
		status = "disabled";
	};

	ufs_card_2_gdsc: qcom,gdsc@1a2004 {
		compatible = "qcom,gdsc";
		regulator-name = "ufs_card_2_gdsc";
		reg = <0x1a2004 0x4>;
		status = "disabled";
	};

	usb30_mp_gdsc: qcom,gdsc@1a6004 {
		compatible = "qcom,gdsc";
		regulator-name = "usb30_mp_gdsc";
		reg = <0x1a6004 0x4>;
		status = "disabled";
	};

	/* GDSCs in Camera CC */
	ife_2_gdsc: qcom,gdsc@ad0f004 {
		compatible = "qcom,gdsc";
		regulator-name = "ife_2_gdsc";
		reg = <0xad0f004 0x4>;
		status = "disabled";
	};

	ife_3_gdsc: qcom,gdsc@ad0f070 {
		compatible = "qcom,gdsc";
		regulator-name = "ife_3_gdsc";
		reg = <0xad0f070 0x4>;
		status = "disabled";
	};
};
+194 −0
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@@ -203,6 +203,8 @@

};

#include "sdmshrike-gdsc.dtsi"

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
@@ -364,5 +366,197 @@
	};
};

&emac_gdsc {
	status = "ok";
};

&pcie_0_gdsc {
	status = "ok";
};

&pcie_1_gdsc {
	status = "ok";
};

&pcie_2_gdsc {
	status = "ok";
};

&pcie_3_gdsc {
	status = "ok";
};

&ufs_card_gdsc {
	status = "ok";
};

&ufs_card_2_gdsc {
	status = "ok";
};

&ufs_phy_gdsc {
	status = "ok";
};

&usb30_prim_gdsc {
	status = "ok";
};

&usb30_sec_gdsc {
	status = "ok";
};

&usb30_mp_gdsc {
	status = "ok";
};

&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc {
	status = "ok";
};

&hlos1_vote_aggre_noc_mmu_tbu1_gdsc {
	status = "ok";
};

&hlos1_vote_aggre_noc_mmu_tbu2_gdsc {
	status = "ok";
};

&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc {
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
	status = "ok";
};

&hlos1_vote_turing_mmu_tbu0_gdsc {
	status = "ok";
};

&hlos1_vote_turing_mmu_tbu1_gdsc {
	status = "ok";
};

&bps_gdsc {
	clock-names = "ahb_clk";
	clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
	parent-supply = <&pm855p_s1_level>;
	qcom,vote-parent-supply-voltage;
	status = "ok";
};

&ipe_0_gdsc {
	clock-names = "ahb_clk";
	clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
	parent-supply = <&pm855p_s1_level>;
	qcom,vote-parent-supply-voltage;
	status = "ok";
};

&ipe_1_gdsc {
	clock-names = "ahb_clk";
	clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
	parent-supply = <&pm855p_s1_level>;
	qcom,vote-parent-supply-voltage;
	status = "ok";
};

&ife_0_gdsc {
	clock-names = "ahb_clk";
	clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
	parent-supply = <&pm855p_s1_level>;
	qcom,vote-parent-supply-voltage;
	status = "ok";
};

&ife_1_gdsc {
	clock-names = "ahb_clk";
	clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
	parent-supply = <&pm855p_s1_level>;
	qcom,vote-parent-supply-voltage;
	status = "ok";
};

&ife_2_gdsc {
	clock-names = "ahb_clk";
	clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
	parent-supply = <&pm855p_s1_level>;
	qcom,vote-parent-supply-voltage;
	status = "ok";
};

&ife_3_gdsc {
	clock-names = "ahb_clk";
	clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
	parent-supply = <&pm855p_s1_level>;
	qcom,vote-parent-supply-voltage;
	status = "ok";
};

&titan_top_gdsc {
	clock-names = "ahb_clk";
	clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
	parent-supply = <&pm855p_s1_level>;
	qcom,vote-parent-supply-voltage;
	status = "ok";
};

&mdss_core_gdsc {
	clock-names = "ahb_clk";
	clocks = <&clock_gcc GCC_DISP_AHB_CLK>;
	parent-supply = <&pm855p_s1_level>;
	qcom,vote-parent-supply-voltage;
	status = "ok";
};

&gpu_cx_gdsc {
	status = "ok";
};

&gpu_gx_gdsc {
	parent-supply = <&pm855_1_s10_level>;
	qcom,vote-parent-supply-voltage;
	status = "ok";
};

&mvsc_gdsc {
	clock-names = "ahb_clk";
	clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
	parent-supply = <&pm855p_s1_level>;
	qcom,vote-parent-supply-voltage;
	status = "ok";
};

&mvs0_gdsc {
	clock-names = "ahb_clk";
	clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
	parent-supply = <&pm855p_s1_level>;
	qcom,vote-parent-supply-voltage;
	status = "ok";
};

&mvs1_gdsc {
	clock-names = "ahb_clk";
	clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
	parent-supply = <&pm855p_s1_level>;
	qcom,vote-parent-supply-voltage;
	status = "ok";
};

&npu_core_gdsc {
	clock-names = "ahb_clk";
	clocks = <&clock_gcc GCC_NPU_CFG_AHB_CLK>;
	status = "ok";
};

#include "sdmshrike-pinctrl.dtsi"
#include "sdmshrike-regulators.dtsi"