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Commit bb233a93 authored by Thomas Petazzoni's avatar Thomas Petazzoni Committed by Gregory CLEMENT
Browse files

arm64: dts: marvell: use new clock binding on Armada AP806 



This commit updates the Marvell AP806 Device Tree description to make
use of the accepted clock Device Tree binding.

Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
parent bf151162

arch/arm64/boot/dts/marvell/armada-ap806.dtsi

+12 −22
Original line number Diff line number Diff line
@@ -179,7 +179,7 @@ 
				#size-cells = <0>;

				cell-index = <0>;

				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&ringclk 2>;

				clocks = <&ap_syscon 3>;

				status = "disabled";

			};
@@ -190,7 +190,7 @@ 
				#size-cells = <0>;

				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;

				timeout-ms = <1000>;

				clocks = <&ringclk 2>;

				clocks = <&ap_syscon 3>;

				status = "disabled";

			};
@@ -200,7 +200,7 @@ 
				reg-shift = <2>;

				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;

				reg-io-width = <1>;

				clocks = <&ringclk 2>;

				clocks = <&ap_syscon 3>;

				status = "disabled";

			};
@@ -210,29 +210,19 @@ 
				reg-shift = <2>;

				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;

				reg-io-width = <1>;

				clocks = <&ringclk 2>;

				clocks = <&ap_syscon 3>;

				status = "disabled";



			};



			dfx-server@6f8000 {

				compatible = "simple-mfd", "syscon";

				reg = <0x6f8000 0x70000>;



				coreclk: clk@204 {

					compatible = "marvell,armada-ap806-core-clock";

			ap_syscon: system-controller@6f4000 {

				compatible = "marvell,ap806-system-controller",

					     "syscon";

				#clock-cells = <1>;

					clock-output-names = "ddr", "ring", "cpu";

				};



				ringclk: clk@250 {

					compatible = "marvell,armada-ap806-ring-clock";

					#clock-cells = <1>;

					clock-output-names = "ring-0", "ring-2",

							     "ring-3", "ring-4",

							     "ring-5";

					clocks = <&coreclk 1>;

				};

				clock-output-names = "ap-cpu-cluster-0",

						     "ap-cpu-cluster-1",

						     "ap-fixed", "ap-mss";

				reg = <0x6f4000 0x1000>;

			};

		};

	};