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Commit baf6332a authored by Nicolas Ferre's avatar Nicolas Ferre Committed by Linus Torvalds
Browse files

atmel_lcdfb: fix pixclock divider calculation 



Fix divider calculation and allow CLKVAL = 0 (divisor 2)

It was not possible to get the clock value 0 (divisor 2) because
the test "<=0" force the BYPASS bit to be activated instead.

[akpm@linux-foundation.org: coding-style fixes]
Signed-off-by: default avatarNicolas Ferre <nicolas.ferre@atmel.com>
Cc: Per Hedblom <per.hedblom@abem.se>
Cc: Roel Kluin <12o3l@tiscali.nl>
Cc: Jan Weber <jw022609@uni-greifswald.de>
Cc: Andrew Victor <linux@maxim.org.za>
Cc: Haavard Skinnemoen <hskinnemoen@atmel.com>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 945185a6

drivers/video/atmel_lcdfb.c

+6 −5
Original line number Diff line number Diff line
@@ -441,14 +441,15 @@ static int atmel_lcdfb_set_par(struct fb_info *info) 


	value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock));



	value = (value / 2) - 1;

	dev_dbg(info->device, "  * programming CLKVAL = 0x%08lx\n", value);



	if (value <= 0) {

	if (value < 2) {

		dev_notice(info->device, "Bypassing pixel clock divider\n");

		lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);

	} else {

		lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, value << ATMEL_LCDC_CLKVAL_OFFSET);

		value = (value / 2) - 1;

		dev_dbg(info->device, "  * programming CLKVAL = 0x%08lx\n",

				value);

		lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1,

				value << ATMEL_LCDC_CLKVAL_OFFSET);

		info->var.pixclock = KHZ2PICOS(clk_value_khz / (2 * (value + 1)));

		dev_dbg(info->device, "  updated pixclk:     %lu KHz\n",

					PICOS2KHZ(info->var.pixclock));