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Commit ba180093 authored by Jon Hunter's avatar Jon Hunter Committed by Rob Herring
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dt-bindings: Correct path for ARM GIC documentation



Commit eb3fcf00 ("dt-bindings: consolidate interrupt controller
bindings") moved the binding documentation for the ARM GIC from
arm/gic.txt to interrupt-controller/arm,gic.txt. However, there are
still some binding documents referring to the old path. Update these
binding documents to use the correct location.

Fixes: eb3fcf00 ("dt-bindings: consolidate interrupt controller bindings")

Signed-off-by: default avatarJon Hunter <jonathanh@nvidia.com>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Acked-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: default avatarRob Herring <robh@kernel.org>
parent f2953a46
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+2 −1
Original line number Diff line number Diff line
@@ -42,7 +42,8 @@ Examples:
Consumer:
========
See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and
Documentation/devicetree/bindings/arm/gic.txt for further details.
Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt for
further details.

An interrupt consumer on an SoC using crossbar will use:
	interrupts = <GIC_SPI request_number interrupt_level>
+1 −1
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ scu:
	see binding for arm/scu.txt

interrupt-controller:
	see binding for arm/gic.txt
	see binding for interrupt-controller/arm,gic.txt

timer:
	see binding for arm/twd.txt
+1 −2
Original line number Diff line number Diff line
@@ -16,8 +16,7 @@ Required properties:
	"mediatek,mt6577-sysirq"
	"mediatek,mt2701-sysirq"
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Use the same format as specified by GIC in
  Documentation/devicetree/bindings/arm/gic.txt
- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
- interrupt-parent: phandle of irq parent for sysirq. The parent must
  use the same interrupt-cells format as GIC.
- reg: Physical base address of the intpol registers and length of memory