Loading arch/arm64/boot/dts/qcom/pms405.dtsi +13 −0 Original line number Diff line number Diff line Loading @@ -103,6 +103,19 @@ reg = <0x900 0x100>; }; pms405_clkdiv: clock-controller@5b00 { compatible = "qcom,spmi-clkdiv"; reg = <0x5b00 0x100>; #clock-cells = <1>; qcom,num-clkdivs = <1>; clock-output-names = "pms405_div_clk1"; clocks = <&clock_rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "xo"; assigned-clocks = <&pms405_clkdiv 1>; assigned-clock-rates = <9600000>; }; /* QCS405 + PMS405 GPIO configuration */ pms405_gpios: pinctrl@c000 { compatible = "qcom,spmi-gpio"; Loading Loading
arch/arm64/boot/dts/qcom/pms405.dtsi +13 −0 Original line number Diff line number Diff line Loading @@ -103,6 +103,19 @@ reg = <0x900 0x100>; }; pms405_clkdiv: clock-controller@5b00 { compatible = "qcom,spmi-clkdiv"; reg = <0x5b00 0x100>; #clock-cells = <1>; qcom,num-clkdivs = <1>; clock-output-names = "pms405_div_clk1"; clocks = <&clock_rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "xo"; assigned-clocks = <&pms405_clkdiv 1>; assigned-clock-rates = <9600000>; }; /* QCS405 + PMS405 GPIO configuration */ pms405_gpios: pinctrl@c000 { compatible = "qcom,spmi-gpio"; Loading