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Commit b9a8ef9d authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: Update the PMIC XO clocks for QCS405"

parents a6ee6ac4 d8a81b88

drivers/clk/qcom/clk-smd-rpm.c

+15 −19
Original line number Diff line number Diff line
@@ -607,14 +607,12 @@ DEFINE_CLK_SMD_RPM(qcs405, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0); 
DEFINE_CLK_SMD_RPM(qcs405, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);

DEFINE_CLK_SMD_RPM(qcs405, bimc_gpu_clk, bimc_gpu_a_clk,

						QCOM_SMD_RPM_MEM_CLK, 0);



/* SMD_XO_BUFFER */

DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs405, bb_clk1, bb_clk1_a, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs405, bb_clk2, bb_clk2_a, 2);

DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs405, rf_clk2, rf_clk2_a, 5);

DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs405, div_clk2, div_clk2_a, 0xc);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs405, bb_clk1_pin, bb_clk1_a_pin, 1);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs405, bb_clk2_pin, bb_clk2_a_pin, 2);

DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs405, ln_bb_clk, ln_bb_clk_a, 8);

DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs405, rf_clk1, rf_clk1_a, 4);

DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs405, div_clk1, div_clk1_a, 0xb);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs405, ln_bb_clk_pin, ln_bb_clk_a_pin, 8);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs405, rf_clk1_pin, rf_clk1_a_pin, 4);



/* Voter clocks */

static DEFINE_CLK_VOTER(pnoc_msmbus_clk, pnoc_clk, LONG_MAX);
@@ -661,18 +659,16 @@ static struct clk_hw *qcs405_clks[] = { 
	[RPM_SMD_BIMC_A_CLK]		= &qcs405_bimc_a_clk.hw,

	[RPM_SMD_QDSS_CLK]		= &qcs405_qdss_clk.hw,

	[RPM_SMD_QDSS_A_CLK]		= &qcs405_qdss_a_clk.hw,

	[RPM_SMD_BB_CLK1]		= &qcs405_bb_clk1.hw,

	[RPM_SMD_BB_CLK1_A]		= &qcs405_bb_clk1_a.hw,

	[RPM_SMD_BB_CLK2]		= &qcs405_bb_clk2.hw,

	[RPM_SMD_BB_CLK2_A]		= &qcs405_bb_clk2_a.hw,

	[RPM_SMD_RF_CLK2]		= &qcs405_rf_clk2.hw,

	[RPM_SMD_RF_CLK2_A]		= &qcs405_rf_clk2_a.hw,

	[RPM_SMD_BB_CLK1_PIN]		= &qcs405_bb_clk1_pin.hw,

	[RPM_SMD_BB_CLK1_A_PIN]		= &qcs405_bb_clk1_a_pin.hw,

	[RPM_SMD_BB_CLK2_PIN]		= &qcs405_bb_clk2_pin.hw,

	[RPM_SMD_BB_CLK2_A_PIN]		= &qcs405_bb_clk2_a_pin.hw,

	[RPM_SMD_DIV_CLK2]		= &qcs405_div_clk2.hw,

	[RPM_SMD_DIV_A_CLK2]		= &qcs405_div_clk2_a.hw,

	[RPM_SMD_RF_CLK1]		= &qcs405_rf_clk1.hw,

	[RPM_SMD_RF_CLK1_A]		= &qcs405_rf_clk1_a.hw,

	[RPM_SMD_RF_CLK1_PIN]		= &qcs405_rf_clk1_pin.hw,

	[RPM_SMD_RF_CLK1_A_PIN]		= &qcs405_rf_clk1_a_pin.hw,

	[RPM_SMD_LN_BB_CLK]		= &qcs405_ln_bb_clk.hw,

	[RPM_SMD_LN_BB_CLK_A]		= &qcs405_ln_bb_clk_a.hw,

	[RPM_SMD_LN_BB_CLK_PIN]		= &qcs405_ln_bb_clk_pin.hw,

	[RPM_SMD_LN_BB_CLK_A_PIN]	= &qcs405_ln_bb_clk_a_pin.hw,

	[RPM_SMD_DIV_CLK1]		= &qcs405_div_clk1.hw,

	[RPM_SMD_DIV_A_CLK1]		= &qcs405_div_clk1_a.hw,

	[RPM_SMD_PNOC_CLK]		= &qcs405_pnoc_clk.hw,

	[RPM_SMD_PNOC_A_CLK]		= &qcs405_pnoc_a_clk.hw,

	[RPM_SMD_CE1_CLK]		= &qcs405_ce1_clk.hw,

include/dt-bindings/clock/qcom,rpmcc.h

+31 −27
Original line number Diff line number Diff line
@@ -107,32 +107,36 @@ 
#define RPM_SMD_CE1_A_CLK			67

#define RPM_SMD_BIMC_GPU_CLK                    68

#define RPM_SMD_BIMC_GPU_A_CLK                  69

#define PNOC_MSMBUS_CLK				70

#define PNOC_MSMBUS_A_CLK			71

#define PNOC_KEEPALIVE_A_CLK			72

#define SNOC_MSMBUS_CLK				73

#define SNOC_MSMBUS_A_CLK			74

#define BIMC_MSMBUS_CLK				75

#define BIMC_MSMBUS_A_CLK			76

#define PNOC_USB_CLK				77

#define PNOC_USB_A_CLK				78

#define SNOC_USB_CLK				79

#define SNOC_USB_A_CLK				80

#define BIMC_USB_CLK				81

#define BIMC_USB_A_CLK				82

#define SNOC_WCNSS_A_CLK			83

#define BIMC_WCNSS_A_CLK			84

#define MCD_CE1_CLK				85

#define QCEDEV_CE1_CLK				86

#define QCRYPTO_CE1_CLK				87

#define QSEECOM_CE1_CLK				88

#define SCM_CE1_CLK				89

#define CXO_SMD_OTG_CLK				90

#define CXO_SMD_LPM_CLK				91

#define CXO_SMD_PIL_PRONTO_CLK			92

#define CXO_SMD_PIL_MSS_CLK			93

#define CXO_SMD_WLAN_CLK			94

#define CXO_SMD_PIL_LPASS_CLK			95

#define CXO_SMD_PIL_CDSP_CLK			96

#define RPM_SMD_LN_BB_CLK			70

#define RPM_SMD_LN_BB_CLK_A			71

#define RPM_SMD_LN_BB_CLK_PIN			72

#define RPM_SMD_LN_BB_CLK_A_PIN			73

#define PNOC_MSMBUS_CLK				74

#define PNOC_MSMBUS_A_CLK			75

#define PNOC_KEEPALIVE_A_CLK			76

#define SNOC_MSMBUS_CLK				77

#define SNOC_MSMBUS_A_CLK			78

#define BIMC_MSMBUS_CLK				79

#define BIMC_MSMBUS_A_CLK			80

#define PNOC_USB_CLK				81

#define PNOC_USB_A_CLK				82

#define SNOC_USB_CLK				83

#define SNOC_USB_A_CLK				84

#define BIMC_USB_CLK				85

#define BIMC_USB_A_CLK				86

#define SNOC_WCNSS_A_CLK			87

#define BIMC_WCNSS_A_CLK			88

#define MCD_CE1_CLK				89

#define QCEDEV_CE1_CLK				90

#define QCRYPTO_CE1_CLK				91

#define QSEECOM_CE1_CLK				92

#define SCM_CE1_CLK				93

#define CXO_SMD_OTG_CLK				94

#define CXO_SMD_LPM_CLK				95

#define CXO_SMD_PIL_PRONTO_CLK			96

#define CXO_SMD_PIL_MSS_CLK			97

#define CXO_SMD_WLAN_CLK			98

#define CXO_SMD_PIL_LPASS_CLK			99

#define CXO_SMD_PIL_CDSP_CLK			100



#endif