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Commit b900b949 authored by Imre Deak's avatar Imre Deak Committed by Daniel Vetter
Browse files

drm/i915: move rps irq enable/disable to i915_irq.c 



The logical place for these functions is in i915_irq.c next to the rest of
PM interrupt handling functions.

No functional change.

Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 20415c5d

drivers/gpu/drm/i915/i915_irq.c

+41 −0
Original line number Diff line number Diff line
@@ -202,11 +202,21 @@ void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) 
	ilk_update_gt_irq(dev_priv, mask, 0);

}



static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)

{

	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;

}



static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)

{

	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;

}



static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)

{

	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;

}



/**

  * snb_update_pm_irq - update GEN6_PMIMR

  * @dev_priv: driver private
@@ -245,6 +255,37 @@ void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) 
	snb_update_pm_irq(dev_priv, mask, 0);

}



void gen6_enable_rps_interrupts(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	spin_lock_irq(&dev_priv->irq_lock);

	WARN_ON(dev_priv->rps.pm_iir);

	gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);

	I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);

	spin_unlock_irq(&dev_priv->irq_lock);

}



void gen6_disable_rps_interrupts(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	I915_WRITE(GEN6_PMINTRMSK, INTEL_INFO(dev_priv)->gen >= 8 ?

		   ~GEN8_PMINTR_REDIRECT_TO_NON_DISP : ~0);

	I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &

				~dev_priv->pm_rps_events);

	/* Complete PM interrupt masking here doesn't race with the rps work

	 * item again unmasking PM interrupts because that is using a different

	 * register (PMIMR) to mask PM interrupts. The only risk is in leaving

	 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */



	spin_lock_irq(&dev_priv->irq_lock);

	dev_priv->rps.pm_iir = 0;

	spin_unlock_irq(&dev_priv->irq_lock);



	I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);

}



/**

 * ibx_display_interrupt_update - update SDEIMR

 * @dev_priv: driver private

drivers/gpu/drm/i915/intel_drv.h

+2 −0
Original line number Diff line number Diff line
@@ -784,6 +784,8 @@ void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); 
void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);

void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);

void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);

void gen6_enable_rps_interrupts(struct drm_device *dev);

void gen6_disable_rps_interrupts(struct drm_device *dev);

void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);

void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);

static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/intel_pm.c

+0 −41
Original line number Diff line number Diff line
@@ -4519,16 +4519,6 @@ void valleyview_set_rps(struct drm_device *dev, u8 val) 
	trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));

}



static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)

{

	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;

}



static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)

{

	return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;

}



static void gen9_disable_rps(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4536,26 +4526,6 @@ static void gen9_disable_rps(struct drm_device *dev) 
	I915_WRITE(GEN6_RC_CONTROL, 0);

}



static void gen6_disable_rps_interrupts(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	I915_WRITE(GEN6_PMINTRMSK, INTEL_INFO(dev_priv)->gen >= 8 ?

		   ~GEN8_PMINTR_REDIRECT_TO_NON_DISP : ~0);

	I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &

				~dev_priv->pm_rps_events);

	/* Complete PM interrupt masking here doesn't race with the rps work

	 * item again unmasking PM interrupts because that is using a different

	 * register (PMIMR) to mask PM interrupts. The only risk is in leaving

	 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */



	spin_lock_irq(&dev_priv->irq_lock);

	dev_priv->rps.pm_iir = 0;

	spin_unlock_irq(&dev_priv->irq_lock);



	I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);

}



static void gen6_disable_rps(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4651,17 +4621,6 @@ int intel_enable_rc6(const struct drm_device *dev) 
	return i915.enable_rc6;

}



static void gen6_enable_rps_interrupts(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	spin_lock_irq(&dev_priv->irq_lock);

	WARN_ON(dev_priv->rps.pm_iir);

	gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);

	I915_WRITE(gen6_pm_iir(dev_priv), dev_priv->pm_rps_events);

	spin_unlock_irq(&dev_priv->irq_lock);

}



static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)

{

	/* All of these values are in units of 50MHz */