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Commit b8fbbafb authored by Subbaraman Narayanamurthy's avatar Subbaraman Narayanamurthy
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power: qpnp-fg-gen4: Disable Rslow compensation for PM8150B v1 



As per the hardware recommendation, disable Rslow compensation
for PM8150B v1 to prevent Rslow flooring.

Change-Id: Ic579450050b2fc47cc20def8e0f1f43d97ef27d4
Signed-off-by: default avatarSubbaraman Narayanamurthy <subbaram@codeaurora.org>
parent 308cb81a

drivers/power/supply/qcom/fg-core.h

+1 −0
Original line number Diff line number Diff line
@@ -257,6 +257,7 @@ enum wa_flags { 
	PMI8998_V1_REV_WA = BIT(0),

	PM660_TSMC_OSC_WA = BIT(1),

	PM8150B_V1_DMA_WA = BIT(2),

	PM8150B_V1_RSLOW_COMP_WA = BIT(3),

};



enum slope_limit_status {

drivers/power/supply/qcom/qpnp-fg-gen4.c

+17 −1
Original line number Diff line number Diff line
@@ -90,6 +90,8 @@ 
#define VBATT_LOW_OFFSET		1

#define PROFILE_LOAD_WORD		65

#define PROFILE_LOAD_OFFSET		0

#define RSLOW_CONFIG_WORD		241

#define RSLOW_CONFIG_OFFSET		0

#define NOM_CAP_WORD			271

#define NOM_CAP_OFFSET			0

#define RCONN_WORD			275
@@ -2638,6 +2640,18 @@ static int fg_gen4_hw_init(struct fg_gen4_chip *chip) 
		}

	}



	if (fg->wa_flags & PM8150B_V1_RSLOW_COMP_WA) {

		val = 0;

		mask = BIT(1);

		rc = fg_sram_masked_write(fg, RSLOW_CONFIG_WORD,

				RSLOW_CONFIG_OFFSET, mask, val, FG_IMA_DEFAULT);

		if (rc < 0) {

			pr_err("Error in writing RSLOW_CONFIG_WORD, rc=%d\n",

				rc);

			return rc;

		}

	}



	rc = restore_cycle_count(chip->counter);

	if (rc < 0) {

		pr_err("Error in restoring cycle_count, rc=%d\n", rc);
@@ -2833,8 +2847,10 @@ static int fg_gen4_parse_dt(struct fg_gen4_chip *chip) 
		fg->version = GEN4_FG;

		fg->use_dma = true;

		fg->sp = pm8150_sram_params;

		if (fg->pmic_rev_id->rev4 == PM8150B_V1P0_REV4)

		if (fg->pmic_rev_id->rev4 == PM8150B_V1P0_REV4) {

			fg->wa_flags |= PM8150B_V1_DMA_WA;

			fg->wa_flags |= PM8150B_V1_RSLOW_COMP_WA;

		}

		break;

	default:

		return -EINVAL;