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Commit b8cd337c authored by Arnd Bergmann's avatar Arnd Bergmann Committed by Gregory CLEMENT
Browse files

ARM: orion: always use MULTI_IRQ_HANDLER 



As a preparation for multiplatform support, this enables
the MULTI_IRQ_HANDLER code unconditionally on dove and
orion5x, and introduces the respective code on mv78xx0,
which did not have it so far. The classic entry-macro.S
files are removed as they are now obsolete.

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
Acked-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
parent 06f3008a

arch/arm/Kconfig

+3 −0
Original line number Diff line number Diff line
@@ -510,6 +510,7 @@ config ARCH_DOVE 
	select CPU_PJ4

	select GENERIC_CLOCKEVENTS

	select MIGHT_HAVE_PCI

	select MULTI_IRQ_HANDLER

	select MVEBU_MBUS

	select PINCTRL

	select PINCTRL_DOVE
@@ -523,6 +524,7 @@ config ARCH_MV78XX0 
	select CPU_FEROCEON

	select GENERIC_CLOCKEVENTS

	select MVEBU_MBUS

	select MULTI_IRQ_HANDLER

	select PCI

	select PLAT_ORION_LEGACY

	help
@@ -536,6 +538,7 @@ config ARCH_ORION5X 
	select CPU_FEROCEON

	select GENERIC_CLOCKEVENTS

	select MVEBU_MBUS

	select MULTI_IRQ_HANDLER

	select PCI

	select PLAT_ORION_LEGACY

	select MULTI_IRQ_HANDLER

arch/arm/mach-dove/include/mach/entry-macro.S

deleted100644 → 0
+0 −33
Original line number Diff line number Diff line 
/*

 * arch/arm/mach-dove/include/mach/entry-macro.S

 *

 * Low-level IRQ helper macros for Marvell Dove platforms

 *

 * This file is licensed under the terms of the GNU General Public

 * License version 2.  This program is licensed "as is" without any

 * warranty of any kind, whether express or implied.

 */



#include <mach/bridge-regs.h>



	.macro  get_irqnr_preamble, base, tmp

	ldr	\base, =IRQ_VIRT_BASE

	.endm



	.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp

	@ check low interrupts

	ldr	\irqstat, [\base, #IRQ_CAUSE_LOW_OFF]

	ldr	\tmp, [\base, #IRQ_MASK_LOW_OFF]

	mov	\irqnr, #31

	ands	\irqstat, \irqstat, \tmp



	@ if no low interrupts set, check high interrupts

	ldreq	\irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]

	ldreq	\tmp, [\base, #IRQ_MASK_HIGH_OFF]

	moveq	\irqnr, #63

	andeqs	\irqstat, \irqstat, \tmp



	@ find first active interrupt source

	clzne	\irqstat, \irqstat

	subne	\irqnr, \irqnr, \irqstat

	.endm

arch/arm/mach-dove/irq.c

+1 −11
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include <linux/irq.h>

#include <linux/gpio.h>

#include <linux/io.h>

#include <asm/exception.h>

#include <asm/mach/arch.h>

#include <plat/irq.h>

#include <asm/mach/irq.h>
@@ -109,14 +110,6 @@ static int __initdata gpio2_irqs[4] = { 
	0,

};



#ifdef CONFIG_MULTI_IRQ_HANDLER

/*

 * Compiling with both non-DT and DT support enabled, will

 * break asm irq handler used by non-DT boards. Therefore,

 * we provide a C-style irq handler even for non-DT boards,

 * if MULTI_IRQ_HANDLER is set.

 */



static void __iomem *dove_irq_base = IRQ_VIRT_BASE;



static asmlinkage void
@@ -139,7 +132,6 @@ __exception_irq_entry dove_legacy_handle_irq(struct pt_regs *regs) 
		return;

	}

}

#endif



void __init dove_init_irq(void)

{
@@ -148,9 +140,7 @@ void __init dove_init_irq(void) 
	orion_irq_init(1, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);

	orion_irq_init(33, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);



#ifdef CONFIG_MULTI_IRQ_HANDLER

	set_handle_irq(dove_legacy_handle_irq);

#endif



	/*

	 * Initialize gpiolib for GPIOs 0-71.

arch/arm/mach-mv78xx0/include/mach/entry-macro.S

deleted100644 → 0
+0 −41
Original line number Diff line number Diff line 
/*

 * arch/arm/mach-mv78xx0/include/mach/entry-macro.S

 *

 * Low-level IRQ helper macros for Marvell MV78xx0 platforms

 *

 * This file is licensed under the terms of the GNU General Public

 * License version 2.  This program is licensed "as is" without any

 * warranty of any kind, whether express or implied.

 */



#include <mach/bridge-regs.h>



	.macro  get_irqnr_preamble, base, tmp

	ldr	\base, =IRQ_VIRT_BASE

	.endm



	.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp

	@ check low interrupts

	ldr	\irqstat, [\base, #IRQ_CAUSE_LOW_OFF]

	ldr	\tmp, [\base, #IRQ_MASK_LOW_OFF]

	mov	\irqnr, #31

	ands	\irqstat, \irqstat, \tmp

	bne	1001f



	@ if no low interrupts set, check high interrupts

	ldr	\irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]

	ldr	\tmp, [\base, #IRQ_MASK_HIGH_OFF]

	mov	\irqnr, #63

	ands	\irqstat, \irqstat, \tmp

	bne	1001f



	@ if no high interrupts set, check error interrupts

	ldr	\irqstat, [\base, #IRQ_CAUSE_ERR_OFF]

	ldr	\tmp, [\base, #IRQ_MASK_ERR_OFF]

	mov	\irqnr, #95

	ands	\irqstat, \irqstat, \tmp



	@ find first active interrupt source

1001:	clzne	\irqstat, \irqstat

	subne	\irqnr, \irqnr, \irqstat

	.endm

arch/arm/mach-mv78xx0/irq.c

+33 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
#include <linux/kernel.h>

#include <linux/irq.h>

#include <linux/io.h>

#include <asm/exception.h>

#include <mach/bridge-regs.h>

#include <plat/orion-gpio.h>

#include <plat/irq.h>
@@ -23,12 +24,44 @@ static int __initdata gpio0_irqs[4] = { 
	IRQ_MV78XX0_GPIO_24_31,

};



static void __iomem *mv78xx0_irq_base = IRQ_VIRT_BASE;



static asmlinkage void

__exception_irq_entry mv78xx0_legacy_handle_irq(struct pt_regs *regs)

{

	u32 stat;



	stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_LOW_OFF);

	stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_LOW_OFF);

	if (stat) {

		unsigned int hwirq = __fls(stat);

		handle_IRQ(hwirq, regs);

		return;

	}

	stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_HIGH_OFF);

	stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_HIGH_OFF);

	if (stat) {

		unsigned int hwirq = 32 + __fls(stat);

		handle_IRQ(hwirq, regs);

		return;

	}

	stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_ERR_OFF);

	stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_ERR_OFF);

	if (stat) {

		unsigned int hwirq = 64 + __fls(stat);

		handle_IRQ(hwirq, regs);

		return;

	}

}



void __init mv78xx0_init_irq(void)

{

	orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);

	orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);

	orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF);



	set_handle_irq(mv78xx0_legacy_handle_irq);



	/*

	 * Initialize gpiolib for GPIOs 0-31.  (The GPIO interrupt mask

	 * registers for core #1 are at an offset of 0x18 from those of