Merge "ARM: dts: Add 895MHz GPU clock support for SM6150" (b8ca820f) · Commits · e / devices / android_kernel_oneplus_sm8150

arch/arm64/boot/dts/qcom/sm6150-gpu.dtsi

+235 −62

Original line number	Diff line number	Diff line
		@@ -33,8 +33,10 @@
		label = "kgsl-3d0";
		compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
		status = "ok";
		reg = <0x5000000 0x40000>;
		reg-names = "kgsl_3d0_reg_memory";
		reg = <0x5000000 0x40000>,
		<0x780000 0x6fff>;
		reg-names = "kgsl_3d0_reg_memory",
		"qfprom_memory";
		interrupts = <0 300 0>;
		interrupt-names = "kgsl_3d0_irq";
		qcom,id = <0>;
		@@ -108,6 +110,8 @@
		/* Context aware jump target power level */
		qcom,ca-target-pwrlevel = <3>;

		qcom,gpu-speed-bin = <0x6004 0x1fe00000 21>;

		/* GPU Mempools */
		qcom,gpu-mempools {
		#address-cells = <1>;
		@@ -140,13 +144,101 @@
		};
		};

		qcom,gpu-pwrlevels {
		/*
		* Speed-bin zero is default speed bin.
		* For rest of the speed bins, speed-bin value
		* is calulated as FMAX/4.8 MHz round up to zero
		* decimal places.
		*/
		qcom,gpu-pwrlevel-bins {
		#address-cells = <1>;
		#size-cells = <0>;

		compatible="qcom,gpu-pwrlevel-bins";

		qcom,gpu-pwrlevels-0 {
		#address-cells = <1>;
		#size-cells = <0>;

		qcom,speed-bin = <0>;

		qcom,initial-pwrlevel = <3>;
		qcom,ca-target-pwrlevel = <3>;

		/* SVS_L1 */
		qcom,gpu-pwrlevel@0 {
		reg = <0>;
		qcom,gpu-freq = <845000000>;
		qcom,bus-freq = <11>;
		qcom,bus-min = <10>;
		qcom,bus-max = <11>;
		};

		/* NOM L1 */
		qcom,gpu-pwrlevel@1 {
		reg = <1>;
		qcom,gpu-freq = <706000000>;
		qcom,bus-freq = <10>;
		qcom,bus-min = <9>;
		qcom,bus-max = <11>;
		};

		/* NOM */
		qcom,gpu-pwrlevel@2 {
		reg = <2>;
		qcom,gpu-freq = <645000000>;
		qcom,bus-freq = <9>;
		qcom,bus-min = <8>;
		qcom,bus-max = <10>;
		};

		/* SVS L1 */
		qcom,gpu-pwrlevel@3 {
		reg = <3>;
		qcom,gpu-freq = <513000000>;
		qcom,bus-freq = <8>;
		qcom,bus-min = <7>;
		qcom,bus-max = <9>;
		};

		/* SVS */
		qcom,gpu-pwrlevel@4 {
		reg = <4>;
		qcom,gpu-freq = <400000000>;
		qcom,bus-freq = <7>;
		qcom,bus-min = <5>;
		qcom,bus-max = <8>;
		};

		/* Low SVS */
		qcom,gpu-pwrlevel@5 {
		reg = <5>;
		qcom,gpu-freq = <290000000>;
		qcom,bus-freq = <4>;
		qcom,bus-min = <4>;
		qcom,bus-max = <5>;
		};

		/* XO */
		qcom,gpu-pwrlevel@6 {
		reg = <6>;
		qcom,gpu-freq = <0>;
		qcom,bus-freq = <0>;
		qcom,bus-min = <0>;
		qcom,bus-max = <0>;
		};
		};

		qcom,gpu-pwrlevels-1 {
		#address-cells = <1>;
		#size-cells = <0>;

		compatible = "qcom,gpu-pwrlevels";
		qcom,speed-bin = <177>;

		/* TURBO */
		qcom,initial-pwrlevel = <3>;
		qcom,ca-target-pwrlevel = <3>;

		/* SVS_L1 */
		qcom,gpu-pwrlevel@0 {
		reg = <0>;
		qcom,gpu-freq = <845000000>;
		@@ -158,7 +250,7 @@
		/* NOM L1 */
		qcom,gpu-pwrlevel@1 {
		reg = <1>;
		qcom,gpu-freq = <745000000>;
		qcom,gpu-freq = <706000000>;
		qcom,bus-freq = <10>;
		qcom,bus-min = <9>;
		qcom,bus-max = <11>;
		@@ -167,7 +259,7 @@
		/* NOM */
		qcom,gpu-pwrlevel@2 {
		reg = <2>;
		qcom,gpu-freq = <700000000>;
		qcom,gpu-freq = <645000000>;
		qcom,bus-freq = <9>;
		qcom,bus-min = <8>;
		qcom,bus-max = <10>;
		@@ -176,7 +268,7 @@
		/* SVS L1 */
		qcom,gpu-pwrlevel@3 {
		reg = <3>;
		qcom,gpu-freq = <550000000>;
		qcom,gpu-freq = <513000000>;
		qcom,bus-freq = <8>;
		qcom,bus-min = <7>;
		qcom,bus-max = <9>;
		@@ -185,7 +277,7 @@
		/* SVS */
		qcom,gpu-pwrlevel@4 {
		reg = <4>;
		qcom,gpu-freq = <435000000>;
		qcom,gpu-freq = <400000000>;
		qcom,bus-freq = <7>;
		qcom,bus-min = <5>;
		qcom,bus-max = <8>;
		@@ -209,6 +301,87 @@
		qcom,bus-max = <0>;
		};
		};

		qcom,gpu-pwrlevels-2 {
		#address-cells = <1>;
		#size-cells = <0>;

		qcom,speed-bin = <187>;

		qcom,initial-pwrlevel = <3>;
		qcom,ca-target-pwrlevel = <4>;

		qcom,gpu-pwrlevel@0 {
		reg = <0>;
		qcom,gpu-freq = <895000000>;
		qcom,bus-freq = <11>;
		qcom,bus-min = <10>;
		qcom,bus-max = <11>;
		};
		/* SVS_L1 */
		qcom,gpu-pwrlevel@1 {
		reg = <1>;
		qcom,gpu-freq = <845000000>;
		qcom,bus-freq = <11>;
		qcom,bus-min = <10>;
		qcom,bus-max = <11>;
		};

		/* NOM L1 */
		qcom,gpu-pwrlevel@2 {
		reg = <2>;
		qcom,gpu-freq = <706000000>;
		qcom,bus-freq = <10>;
		qcom,bus-min = <9>;
		qcom,bus-max = <11>;
		};

		/* NOM */
		qcom,gpu-pwrlevel@3 {
		reg = <3>;
		qcom,gpu-freq = <645000000>;
		qcom,bus-freq = <9>;
		qcom,bus-min = <8>;
		qcom,bus-max = <10>;
		};

		/* SVS L1 */
		qcom,gpu-pwrlevel@4 {
		reg = <4>;
		qcom,gpu-freq = <513000000>;
		qcom,bus-freq = <8>;
		qcom,bus-min = <7>;
		qcom,bus-max = <9>;
		};

		/* SVS */
		qcom,gpu-pwrlevel@5 {
		reg = <5>;
		qcom,gpu-freq = <400000000>;
		qcom,bus-freq = <7>;
		qcom,bus-min = <5>;
		qcom,bus-max = <8>;
		};

		/* Low SVS */
		qcom,gpu-pwrlevel@6 {
		reg = <6>;
		qcom,gpu-freq = <290000000>;
		qcom,bus-freq = <4>;
		qcom,bus-min = <4>;
		qcom,bus-max = <5>;
		};

		/* XO */
		qcom,gpu-pwrlevel@7 {
		reg = <7>;
		qcom,gpu-freq = <0>;
		qcom,bus-freq = <0>;
		qcom,bus-min = <0>;
		qcom,bus-max = <0>;
		};
		};
		};
		};

		kgsl_msm_iommu: qcom,kgsl-iommu@0x050a0000 {

drivers/gpu/msm/adreno_a6xx.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -2656,6 +2656,7 @@ static const struct {
		void (func)(struct adreno_device adreno_dev);
		} a6xx_efuse_funcs[] = {
		{ adreno_is_a615, a6xx_efuse_speed_bin },
		{ adreno_is_a608, a6xx_efuse_speed_bin },
		};

		static void a6xx_check_features(struct adreno_device *adreno_dev)