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Commit b6c7fbcd authored by Jilai Wang's avatar Jilai Wang
Browse files

msm: npu: Enable npu cti/apb/atb/perf_cnt clocks 



Enable npu cti/apb/atb/perf_cnt clocks to support QDSS hw events.

Change-Id: I2b2b84cd5780ea9f03f4666f8991ccd145e682c0
Signed-off-by: default avatarJilai Wang <jilaiw@codeaurora.org>
parent 829ed9cc

drivers/media/platform/msm/npu/npu_common.h

+1 −1
Original line number Diff line number Diff line
@@ -67,7 +67,7 @@ 
#define ROW_BYTES 16

#define GROUP_BYTES 4



#define NUM_TOTAL_CLKS          19

#define NUM_TOTAL_CLKS          20

#define NPU_MAX_REGULATOR_NUM	2

#define NPU_MAX_DT_NAME_LEN	    21

#define NPU_MAX_PWRLEVELS		7

drivers/media/platform/msm/npu/npu_dev.c

+30 −41
Original line number Diff line number Diff line
@@ -64,7 +64,6 @@ static ssize_t npu_store_pwr_state(struct device *dev, 
static void npu_suspend_devbw(struct npu_device *npu_dev);

static void npu_resume_devbw(struct npu_device *npu_dev);

static bool npu_is_post_clock(const char *clk_name);

static bool npu_is_exclude_clock(const char *clk_name);

static bool npu_is_exclude_rate_clock(const char *clk_name);

static int npu_get_max_state(struct thermal_cooling_device *cdev,

				 unsigned long *state);
@@ -99,13 +98,14 @@ static void __exit npu_exit(void); 
 * -------------------------------------------------------------------------

 */

static const char * const npu_clock_order[] = {

	"qdss_clk",

	"at_clk",

	"trig_clk",

	"armwic_core_clk",

	"cal_dp_clk_src",

	"cal_dp_clk",

	"cal_dp_cdc_clk",

	"conf_noc_ahb_clk",

	"comp_noc_axi_clk",

	"npu_core_clk_src",

	"npu_core_clk",

	"npu_core_cti_clk",

	"npu_core_apb_clk",
@@ -125,19 +125,14 @@ static const char * const npu_post_clocks[] = { 
	"npu_cpc_timer_clk"

};



static const char * const npu_exclude_clocks[] = {

	"npu_core_clk_src",

	"cal_dp_clk_src",

	"perf_cnt_clk",

	"npu_core_cti_clk",

	"npu_core_apb_clk",

	"npu_core_atb_clk"

};



static const char * const npu_exclude_rate_clocks[] = {

	"qdss_clk",

	"at_clk",

	"trig_clk",

	"sleep_clk",

	"xo_clk",

	"conf_noc_ahb_clk",

	"comp_noc_axi_clk",

	"npu_core_cti_clk",

	"npu_core_apb_clk",

	"npu_core_atb_clk",
@@ -354,7 +349,6 @@ static int npu_set_power_level(struct npu_device *npu_dev) 
	struct npu_pwrctrl *pwr = &npu_dev->pwrctrl;

	struct npu_pwrlevel *pwrlevel;

	int i, ret = 0;

	long clk_rate = 0;

	uint32_t pwr_level_to_set;



	if (!pwr->pwr_vote_num) {
@@ -388,13 +382,12 @@ static int npu_set_power_level(struct npu_device *npu_dev) 
		pr_debug("requested rate of clock [%s] to [%ld]\n",

			npu_dev->core_clks[i].clk_name, pwrlevel->clk_freq[i]);



		pr_debug("actual round clk rate [%ld]\n", clk_rate);



		ret = clk_set_rate(npu_dev->core_clks[i].clk, clk_rate);

		ret = clk_set_rate(npu_dev->core_clks[i].clk,

			pwrlevel->clk_freq[i]);

		if (ret) {

			pr_debug("clk_set_rate %s to %ld failed with %d\n",

				npu_dev->core_clks[i].clk_name,

				clk_rate, ret);

				pwrlevel->clk_freq[i], ret);

			break;

		}

	}
@@ -491,20 +484,6 @@ static bool npu_is_post_clock(const char *clk_name) 
	return ret;

}



static bool npu_is_exclude_clock(const char *clk_name)

{

	int ret = false;

	int i;



	for (i = 0; i < ARRAY_SIZE(npu_exclude_clocks); i++) {

		if (!strcmp(clk_name, npu_exclude_clocks[i])) {

			ret = true;

			break;

		}

	}

	return ret;

}



static bool npu_is_exclude_rate_clock(const char *clk_name)

{

	int ret = false;
@@ -536,10 +515,7 @@ static int npu_enable_core_clocks(struct npu_device *npu_dev, bool post_pil) 
				continue;

		}



		if (npu_is_exclude_clock(core_clks[i].clk_name))

			continue;



		pr_debug("enabling clock [%s]\n", core_clks[i].clk_name);

		pr_debug("enabling clock %s\n", core_clks[i].clk_name);



		rc = clk_prepare_enable(core_clks[i].clk);

		if (rc) {
@@ -551,16 +527,31 @@ static int npu_enable_core_clocks(struct npu_device *npu_dev, bool post_pil) 
		if (npu_is_exclude_rate_clock(core_clks[i].clk_name))

			continue;



		pr_debug("setting rate of clock [%s] to [%ld]\n",

		pr_debug("setting rate of clock %s to %ld\n",

			core_clks[i].clk_name, pwrlevel->clk_freq[i]);



		rc = clk_set_rate(core_clks[i].clk,

			pwrlevel->clk_freq[i]);

		/* not fatal error, keep using previous clk rate */

		if (rc) {

			pr_debug("clk_set_rate %s to %ld failed\n",

			pr_err("clk_set_rate %s to %ld failed\n",

				core_clks[i].clk_name,

				pwrlevel->clk_freq[i]);

			break;

			rc = 0;

		}

	}



	if (rc) {

		for (i--; i >= 0; i--) {

			if (post_pil) {

				if (!npu_is_post_clock(core_clks[i].clk_name))

					continue;

			} else {

				if (npu_is_post_clock(core_clks[i].clk_name))

					continue;

			}

			pr_debug("disabling clock %s\n", core_clks[i].clk_name);

			clk_disable_unprepare(core_clks[i].clk);

		}

	}
@@ -573,14 +564,12 @@ static void npu_disable_core_clocks(struct npu_device *npu_dev) 
	struct npu_clk *core_clks = npu_dev->core_clks;



	for (i = (npu_dev->core_clk_num)-1; i >= 0 ; i--) {

		if (npu_is_exclude_clock(core_clks[i].clk_name))

			continue;

		if (npu_dev->host_ctx.fw_state == FW_DISABLED) {

			if (npu_is_post_clock(npu_dev->core_clks[i].clk_name))

				continue;

		}



		pr_debug("disabling clock [%s]\n", core_clks[i].clk_name);

		pr_debug("disabling clock %s\n", core_clks[i].clk_name);

		clk_disable_unprepare(core_clks[i].clk);

	}

}