Commit b68fb787 authored Mar 09, 2017 by Jerome Brunet Committed by Michael Turquette Mar 27, 2017

clk: meson: mpll: correct N2 maximum value



Gxbb datasheet says N2 maximum value is 127 but the register field is
9 bits wide, the maximum value should 511.

Test shows value greater than 127, all the way to 511, works well

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20170309104154.28295-9-jbrunet@baylibre.com

parent b778f745

drivers/clk/meson/clk-mpll.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -68,7 +68,7 @@
		#define SDM_MIN 1
		#define SDM_MAX 16383
		#define N2_MIN 4
		#define N2_MAX 127
		#define N2_MAX 511

		#define to_meson_clk_mpll(_hw) container_of(_hw, struct meson_clk_mpll, hw)