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Commit b64f87c1 authored by Becky Bruce's avatar Becky Bruce Committed by Paul Mackerras
Browse files

[POWERPC] Avoid unpaired stwcx. on some processors 



The context switch code in the kernel issues a dummy stwcx. to clear the
reservation, as recommended by the architecture.  However, some processors
can have issues if this stwcx to address A occurs while the reservation
is already held to a different address B.  To avoid this problem, the dummy
stwcx. needs to be paired with a dummy lwarx to the same address.

This adds the dummy lwarx, and creates a cpu feature bit to indicate
which cpus are affected.  Tested on mpc8641_hpcn_defconfig in
arch/powerpc; build tested in arch/ppc.

Signed-off-by: default avatarBecky Bruce <becky.bruce@freescale.com>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent 64c911a3

arch/powerpc/kernel/entry_32.S

+6 −0
Original line number Diff line number Diff line
@@ -251,6 +251,9 @@ syscall_exit_cont: 
	bne-	2f

1:

#endif /* CONFIG_44x */

BEGIN_FTR_SECTION

	lwarx	r7,0,r1

END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)

	stwcx.	r0,0,r1			/* to clear the reservation */

	lwz	r4,_LINK(r1)

	lwz	r5,_CCR(r1)
@@ -717,6 +720,9 @@ restore: 
	mtctr	r11



	PPC405_ERR77(0,r1)

BEGIN_FTR_SECTION

	lwarx	r11,0,r1

END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)

	stwcx.	r0,0,r1			/* to clear the reservation */



#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))

arch/ppc/kernel/entry.S

+6 −0
Original line number Diff line number Diff line
@@ -251,6 +251,9 @@ syscall_exit_cont: 
	bne-	2f

1:

#endif /* CONFIG_44x */

BEGIN_FTR_SECTION

	lwarx	r7,0,r1

END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)

	stwcx.	r0,0,r1			/* to clear the reservation */

	lwz	r4,_LINK(r1)

	lwz	r5,_CCR(r1)
@@ -713,6 +716,9 @@ restore: 
	mtctr	r11



	PPC405_ERR77(0,r1)

BEGIN_FTR_SECTION

	lwarx	r11,0,r1

END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)

	stwcx.	r0,0,r1			/* to clear the reservation */



#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))

include/asm-powerpc/cputable.h

+12 −10
Original line number Diff line number Diff line
@@ -138,6 +138,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, 
#define CPU_FTR_FPU_UNAVAILABLE		ASM_CONST(0x0000000000800000)

#define CPU_FTR_UNIFIED_ID_CACHE	ASM_CONST(0x0000000001000000)

#define CPU_FTR_SPE			ASM_CONST(0x0000000002000000)

#define CPU_FTR_NEED_PAIRED_STWCX	ASM_CONST(0x0000000004000000)



/*

 * Add the 64-bit processor unique features in the top half of the word;
@@ -261,25 +262,25 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, 
#define CPU_FTRS_7450_20	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_7450_21	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_7450_23	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)

#define CPU_FTRS_7455_1	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \

	    CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)

#define CPU_FTRS_7455_20	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
@@ -289,31 +290,32 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, 
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_7447_10	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE)

	    CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \

	    CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_7447	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_7447A	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_7448	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \

	    CPU_FTR_PPC_LE)

	    CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_82XX	(CPU_FTR_COMMON | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)

#define CPU_FTRS_G2_LE	(CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \