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Commit b62adbd1 authored by Nick Hoath's avatar Nick Hoath Committed by Daniel Vetter
Browse files

drm/i915/bxt: Move WaForceEnableNonCoherent to Skylake only 



Signed-off-by: default avatarNick Hoath <nicholas.hoath@intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 27a1b688

drivers/gpu/drm/i915/intel_ringbuffer.c

+11 −11
Original line number Diff line number Diff line
@@ -951,17 +951,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) 
				  GEN9_ENABLE_YV12_BUGFIX);

	}



	if (INTEL_REVID(dev) <= SKL_REVID_D0) {

		/*

		 *Use Force Non-Coherent whenever executing a 3D context. This

		 * is a workaround for a possible hang in the unlikely event

		 * a TLB invalidation occurs during a PSD flush.

		 */

		/* WaForceEnableNonCoherent:skl */

		WA_SET_BIT_MASKED(HDC_CHICKEN0,

				  HDC_FORCE_NON_COHERENT);

	}



	/* Wa4x4STCOptimizationDisable:skl */

	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
@@ -1039,6 +1028,17 @@ static int skl_init_workarounds(struct intel_engine_cs *ring) 
		WA_SET_BIT_MASKED(HIZ_CHICKEN,

				  BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);



	if (INTEL_REVID(dev) <= SKL_REVID_D0) {

		/*

		 *Use Force Non-Coherent whenever executing a 3D context. This

		 * is a workaround for a possible hang in the unlikely event

		 * a TLB invalidation occurs during a PSD flush.

		 */

		/* WaForceEnableNonCoherent:skl */

		WA_SET_BIT_MASKED(HDC_CHICKEN0,

				  HDC_FORCE_NON_COHERENT);

	}



	return skl_tune_iz_hashing(ring);

}