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Commit b5cd8917 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 

Pull clk fixes from Stephen Boyd:
 "This is the first batch of clk driver fixes for this release.

  We have a handful of fixes for the uniphier clk driver that was
  introduced recently, as well as Kconfig option hiding, module
  autoloading markings, and a few fixes for clk_hw based registration
  patches that went in this merge window"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: at91: Fix a return value in case of error
  clk: uniphier: rename MIO clock to SD clock for Pro5, PXs2, LD20 SoCs
  clk: uniphier: fix memory overrun bug
  clk: hi6220: use CLK_OF_DECLARE_DRIVER for sysctrl and mediactrl clock init
  clk: mvebu: armada-37xx-periph: Fix the clock gate flag
  clk: bcm2835: Clamp the PLL's requested rate to the hardware limits.
  clk: max77686: fix number of clocks setup for clk_hw based registration
  clk: mvebu: armada-37xx-periph: Fix the clock provider registration
  clk: core: add __init decoration for CLK_OF_DECLARE_DRIVER function
  clk: mediatek: Add hardware dependency
  clk: samsung: clk-exynos-audss: Fix module autoload
  clk: uniphier: fix type of variable passed to regmap_read()
  clk: uniphier: add system clock support for sLD3 SoC
parents 1ce5bdb8 91bbc174

Documentation/devicetree/bindings/clock/uniphier-clock.txt

+8 −8
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ Example: 
		reg = <0x61840000 0x4000>;



		clock {

			compatible = "socionext,uniphier-ld20-clock";

			compatible = "socionext,uniphier-ld11-clock";

			#clock-cells = <1>;

		};
@@ -43,8 +43,8 @@ Provided clocks: 
21: USB3 ch1 PHY1





Media I/O (MIO) clock

---------------------

Media I/O (MIO) clock, SD clock

-------------------------------



Required properties:

- compatible: should be one of the following:
@@ -52,10 +52,10 @@ Required properties: 
    "socionext,uniphier-ld4-mio-clock"  - for LD4 SoC.

    "socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.

    "socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.

    "socionext,uniphier-pro5-mio-clock" - for Pro5 SoC.

    "socionext,uniphier-pxs2-mio-clock" - for PXs2/LD6b SoC.

    "socionext,uniphier-pro5-sd-clock"  - for Pro5 SoC.

    "socionext,uniphier-pxs2-sd-clock"  - for PXs2/LD6b SoC.

    "socionext,uniphier-ld11-mio-clock" - for LD11 SoC.

    "socionext,uniphier-ld20-mio-clock" - for LD20 SoC.

    "socionext,uniphier-ld20-sd-clock"  - for LD20 SoC.

- #clock-cells: should be 1.



Example:
@@ -66,7 +66,7 @@ Example: 
		reg = <0x59810000 0x800>;



		clock {

			compatible = "socionext,uniphier-ld20-mio-clock";

			compatible = "socionext,uniphier-ld11-mio-clock";

			#clock-cells = <1>;

		};
@@ -112,7 +112,7 @@ Example: 
		reg = <0x59820000 0x200>;



		clock {

			compatible = "socionext,uniphier-ld20-peri-clock";

			compatible = "socionext,uniphier-ld11-peri-clock";

			#clock-cells = <1>;

		};

drivers/clk/at91/clk-programmable.c

+1 −1
Original line number Diff line number Diff line
@@ -203,7 +203,7 @@ at91_clk_register_programmable(struct regmap *regmap, 
	ret = clk_hw_register(NULL, &prog->hw);

	if (ret) {

		kfree(prog);

		hw = &prog->hw;

		hw = ERR_PTR(ret);

	}



	return hw;

drivers/clk/bcm/clk-bcm2835.c

+4 −7
Original line number Diff line number Diff line
@@ -502,8 +502,12 @@ static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate, 
static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate,

				   unsigned long *parent_rate)

{

	struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);

	const struct bcm2835_pll_data *data = pll->data;

	u32 ndiv, fdiv;



	rate = clamp(rate, data->min_rate, data->max_rate);



	bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv);



	return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1);
@@ -608,13 +612,6 @@ static int bcm2835_pll_set_rate(struct clk_hw *hw, 
	u32 ana[4];

	int i;



	if (rate < data->min_rate || rate > data->max_rate) {

		dev_err(cprman->dev, "%s: rate out of spec: %lu vs (%lu, %lu)\n",

			clk_hw_get_name(hw), rate,

			data->min_rate, data->max_rate);

		return -EINVAL;

	}



	if (rate > data->max_fb_rate) {

		use_fb_prediv = true;

		rate /= 2;

drivers/clk/clk-max77686.c

+1 −0
Original line number Diff line number Diff line
@@ -216,6 +216,7 @@ static int max77686_clk_probe(struct platform_device *pdev) 
		return -EINVAL;

	}



	drv_data->num_clks = num_clks;

	drv_data->max_clk_data = devm_kcalloc(dev, num_clks,

					      sizeof(*drv_data->max_clk_data),

					      GFP_KERNEL);

drivers/clk/hisilicon/clk-hi6220.c

+2 −2
Original line number Diff line number Diff line
@@ -195,7 +195,7 @@ static void __init hi6220_clk_sys_init(struct device_node *np) 
	hi6220_clk_register_divider(hi6220_div_clks_sys,

			ARRAY_SIZE(hi6220_div_clks_sys), clk_data);

}

CLK_OF_DECLARE(hi6220_clk_sys, "hisilicon,hi6220-sysctrl", hi6220_clk_sys_init);

CLK_OF_DECLARE_DRIVER(hi6220_clk_sys, "hisilicon,hi6220-sysctrl", hi6220_clk_sys_init);





/* clocks in media controller */
@@ -252,7 +252,7 @@ static void __init hi6220_clk_media_init(struct device_node *np) 
	hi6220_clk_register_divider(hi6220_div_clks_media,

				ARRAY_SIZE(hi6220_div_clks_media), clk_data);

}

CLK_OF_DECLARE(hi6220_clk_media, "hisilicon,hi6220-mediactrl", hi6220_clk_media_init);

CLK_OF_DECLARE_DRIVER(hi6220_clk_media, "hisilicon,hi6220-mediactrl", hi6220_clk_media_init);





/* clocks in pmctrl */