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Commit b5094e62 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
Browse files

Merge "msm: ipa3: Update IPA4.5 resource group configs"

parents a6d0452e 07c18dc2

drivers/platform/msm/ipa/ipa_v3/ipa_utils.c

+65 −68
Original line number Diff line number Diff line
@@ -174,7 +174,8 @@ 
#define IPA_v4_2_DST_GROUP_MAX		(1)



#define IPA_v4_5_MHI_GROUP_PCIE		(0)

#define IPA_v4_5_GROUP_UL_DL		(1)

#define IPA_v4_5_GROUP_UL_DL_DST	(0)

#define IPA_v4_5_GROUP_UL_DL_SRC	(1)

#define IPA_v4_5_MHI_GROUP_DDR		(1)

#define IPA_v4_5_MHI_GROUP_DMA		(2)

#define IPA_v4_5_MHI_GROUP_QDSS		(3)
@@ -280,7 +281,7 @@ static const struct rsrc_min_max ipa3_rsrc_src_grp_config 
		{14, 14}, {16, 16}, {5, 5}, {5, 5}, {0, 0}, {8, 8} },

	},

	[IPA_3_5] = {

		/* LWA_DL  UL_DL    not used  UC_RX_Q, other are invalid */

		/* LWA_DL  UL_DL    unused  UC_RX_Q, other are invalid */

		[IPA_v3_5_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = {

		{0, 0}, {1, 255}, {0, 0}, {1, 255}, {0, 0}, {0, 0} },

		[IPA_v3_5_RSRC_GRP_TYPE_SRS_DESCRIPTOR_LISTS] = {
@@ -293,7 +294,7 @@ static const struct rsrc_min_max ipa3_rsrc_src_grp_config 
		{0, 0}, {20, 20}, {0, 0}, {14, 14}, {0, 0}, {0, 0} },

	},

	[IPA_3_5_MHI] = {

		/* PCIE  DDR     DMA  not used, other are invalid */

		/* PCIE  DDR     DMA  unused, other are invalid */

		[IPA_v3_5_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = {

		{4, 4}, {5, 5}, {1, 1}, {0, 0}, {0, 0}, {0, 0} },

		[IPA_v3_5_RSRC_GRP_TYPE_SRS_DESCRIPTOR_LISTS] = {
@@ -306,7 +307,7 @@ static const struct rsrc_min_max ipa3_rsrc_src_grp_config 
		{14, 14}, {14, 14}, {14, 14}, {0, 0}, {0, 0}, {0, 0} },

	},

	[IPA_3_5_1] = {

		/* LWA_DL  UL_DL    not used  UC_RX_Q, other are invalid */

		/* LWA_DL  UL_DL    unused  UC_RX_Q, other are invalid */

		[IPA_v3_5_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = {

		{1, 255}, {1, 255}, {0, 0}, {1, 255}, {0, 0}, {0, 0} },

		[IPA_v3_5_RSRC_GRP_TYPE_SRS_DESCRIPTOR_LISTS] = {
@@ -319,7 +320,7 @@ static const struct rsrc_min_max ipa3_rsrc_src_grp_config 
		{14, 14}, {20, 20}, {0, 0}, {14, 14}, {0, 0}, {0, 0} },

	},

	[IPA_4_0] = {

		/* LWA_DL  UL_DL    not used  UC_RX_Q, other are invalid */

		/* LWA_DL  UL_DL    unused  UC_RX_Q, other are invalid */

		[IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = {

		{1, 255}, {1, 255}, {0, 0}, {1, 255}, {0, 0}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_SRS_DESCRIPTOR_LISTS] = {
@@ -332,7 +333,7 @@ static const struct rsrc_min_max ipa3_rsrc_src_grp_config 
		{14, 14}, {20, 20}, {0, 0}, {14, 14}, {0, 0}, {0, 0} },

	},

	[IPA_4_0_MHI] = {

		/* PCIE  DDR     DMA  not used, other are invalid */

		/* PCIE  DDR     DMA  unused, other are invalid */

		[IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = {

		{4, 4}, {5, 5}, {1, 1}, {0, 0}, {0, 0}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_SRS_DESCRIPTOR_LISTS] = {
@@ -345,7 +346,7 @@ static const struct rsrc_min_max ipa3_rsrc_src_grp_config 
		{14, 14}, {14, 14}, {14, 14}, {0, 0}, {0, 0}, {0, 0} },

	},

	[IPA_4_1] = {

		/* LWA_DL  UL_DL    not used  UC_RX_Q, other are invalid */

		/* LWA_DL  UL_DL    unused  UC_RX_Q, other are invalid */

		[IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = {

		{1, 63}, {1, 63}, {0, 0}, {1, 63}, {0, 0}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_SRS_DESCRIPTOR_LISTS] = {
@@ -371,9 +372,7 @@ static const struct rsrc_min_max ipa3_rsrc_src_grp_config 
		{5, 5}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },

	},

	[IPA_4_5] = {

		/* not used  UL_DL  not used  not used  UC_RX_Q

		 * other are invalid

		 */

		/* unused  UL_DL_SRC  unused  unused  UC_RX_Q N/A */

		[IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = {

		{0, 0}, {1, 63}, {0, 0}, {0, 0}, {1, 63}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_SRS_DESCRIPTOR_LISTS] = {
@@ -386,7 +385,7 @@ static const struct rsrc_min_max ipa3_rsrc_src_grp_config 
		{0, 0}, {24, 24}, {0, 0}, {0, 0}, {8, 8}, {0, 0} },

	},

	[IPA_4_5_MHI] = {

		/* PCIE  DDR  DMA  QDSS  not used  other are invalid */

		/* PCIE  DDR  DMA  QDSS  unused  N/A  N/A */

		[IPA_v4_0_RSRC_GRP_TYPE_SRC_PKT_CONTEXTS] = {

		{3, 8}, {4, 11}, {1, 1}, {1, 1}, {0, 0}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_SRS_DESCRIPTOR_LISTS] = {
@@ -461,14 +460,14 @@ static const struct rsrc_min_max ipa3_rsrc_dst_grp_config 
		{1, 63}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },

	},

	[IPA_4_5] = {

		/* not-used UL/DL/DPL not-used not-used uC other are invalid */

		/* UL/DL/DPL_DST unused unused unused uC N/A */

		[IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = {

		{0, 0}, {5, 5}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },

		{16, 16}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = {

		{0, 0}, {1, 63}, {0, 0}, {0, 0}, {0, 2}, {0, 0} },

		{2, 63}, {0, 0}, {0, 0}, {0, 0}, {0, 2}, {0, 0} },

	},

	[IPA_4_5_MHI] = {

		/* PCIE/DPL  DDR  DMA/CV2X  QDSS  uC  other are invalid */

		/* PCIE/DPL  DDR  DMA/CV2X  QDSS  uC  N/A */

		[IPA_v4_0_RSRC_GRP_TYPE_DST_DATA_SECTORS] = {

		{16, 16}, {5, 5}, {2, 2}, {2, 2}, {0, 0}, {0, 0} },

		[IPA_v4_0_RSRC_GRP_TYPE_DST_DPS_DMARS] = {
@@ -479,7 +478,7 @@ static const struct rsrc_min_max ipa3_rsrc_dst_grp_config 
static const struct rsrc_min_max ipa3_rsrc_rx_grp_config

	[IPA_VER_MAX][IPA_RSRC_GRP_TYPE_RX_MAX][IPA_GROUP_MAX] = {

	[IPA_3_0] = {

		/* UL	DL	DIAG	DMA	Unused	uC Rx */

		/* UL	DL	DIAG	DMA	unused	uC Rx */

		[IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = {

		{16, 16}, {24, 24}, {8, 8}, {8, 8}, {0, 0}, {8, 8} },

	},
@@ -499,7 +498,7 @@ static const struct rsrc_min_max ipa3_rsrc_rx_grp_config 
		{3, 3}, {7, 7}, {0, 0}, {2, 2}, {0, 0}, {0, 0} },

	},

	[IPA_4_0] = {

		/* LWA_DL UL_DL	not used UC_RX_Q, other are invalid */

		/* LWA_DL UL_DL	unused UC_RX_Q, other are invalid */

		[IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = {

		{3, 3}, {7, 7}, {0, 0}, {2, 2}, {0, 0}, {0, 0} },

	},
@@ -509,7 +508,7 @@ static const struct rsrc_min_max ipa3_rsrc_rx_grp_config 
		{ 3, 3 }, { 7, 7 }, { 2, 2 }, { 0, 0 }, { 0, 0 }, { 0, 0 } },

	},

	[IPA_4_1] = {

		/* LWA_DL UL_DL	not used UC_RX_Q, other are invalid */

		/* LWA_DL UL_DL	unused UC_RX_Q, other are invalid */

		[IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = {

		{3, 3}, {7, 7}, {0, 0}, {2, 2}, {0, 0}, {0, 0} },

	},
@@ -519,14 +518,12 @@ static const struct rsrc_min_max ipa3_rsrc_rx_grp_config 
		{4, 4}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },

	},

	[IPA_4_5] = {

		/* not used  UL_DL  not used  not used  UC_RX_Q

		 * other are invalid

		 */

		/* unused  UL_DL  unused unused  UC_RX_Q  N/A */

		[IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = {

		{0, 0}, {3, 3}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },

	},

	[IPA_4_5_MHI] = {

		/* PCIE  DDR  DMA  QDSS  not used  other are invalid */

		/* PCIE  DDR  DMA  QDSS  unused  N/A */

		[IPA_RSRC_GRP_TYPE_RX_HPS_CMDQ] = {

		{ 3, 3 }, {3, 3}, {3, 3}, {3, 3}, {0, 0}, { 0, 0 } },

	},
@@ -536,7 +533,7 @@ static const struct rsrc_min_max ipa3_rsrc_rx_grp_config 
static const u32 ipa3_rsrc_rx_grp_hps_weight_config

	[IPA_VER_MAX][IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_MAX][IPA_GROUP_MAX] = {

	[IPA_3_0] = {

		/* UL	DL	DIAG	DMA	Unused	uC Rx */

		/* UL	DL	DIAG	DMA	unused	uC Rx */

		[IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] = { 0, 0, 0, 0, 0, 0 },

	},

	[IPA_3_5] = {
@@ -552,7 +549,7 @@ static const u32 ipa3_rsrc_rx_grp_hps_weight_config 
		[IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] = { 1, 1, 1, 1, 0, 0 },

	},

	[IPA_4_0] = {

		/* LWA_DL UL_DL	not used UC_RX_Q, other are invalid */

		/* LWA_DL UL_DL	unused UC_RX_Q N/A */

		[IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] = { 1, 1, 1, 1, 0, 0 },

	},

	[IPA_4_0_MHI] = {
@@ -560,7 +557,7 @@ static const u32 ipa3_rsrc_rx_grp_hps_weight_config 
		[IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] = { 3, 5, 1, 1, 0, 0 },

	},

	[IPA_4_1] = {

		/* LWA_DL UL_DL	not used UC_RX_Q, other are invalid */

		/* LWA_DL UL_DL	unused UC_RX_Q, other are invalid */

		[IPA_RSRC_GRP_TYPE_RX_HPS_WEIGHT_CONFIG] = { 1, 1, 1, 1, 0, 0 },

	},

};
@@ -2043,165 +2040,165 @@ static const struct ipa_ep_configuration ipa3_ep_mapping 


	/* IPA_4_5 */

	[IPA_4_5][IPA_CLIENT_WLAN1_PROD]          = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_SRC,

			true,

			IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP,

			QMB_MASTER_SELECT_DDR,

			{ 9, 12, 8, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 } },

	[IPA_4_5][IPA_CLIENT_USB_PROD]            = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_SRC,

			true,

			IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP,

			QMB_MASTER_SELECT_DDR,

			{ 0, 11, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5][IPA_CLIENT_APPS_LAN_PROD]	  = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_SRC,

			false,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 11, 14, 10, 16, IPA_EE_AP, GSI_SMART_PRE_FETCH, 2 } },

	[IPA_4_5][IPA_CLIENT_APPS_WAN_PROD]	  = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_SRC,

			true,

			IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP,

			QMB_MASTER_SELECT_DDR,

			{ 2, 7, 16, 32, IPA_EE_AP, GSI_SMART_PRE_FETCH, 8 } },

	[IPA_4_5][IPA_CLIENT_APPS_CMD_PROD]	  = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_SRC,

			false,

			IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,

			QMB_MASTER_SELECT_DDR,

			{ 7, 9, 20, 24, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5][IPA_CLIENT_ODU_PROD]            = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_SRC,

			true,

			IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP,

			QMB_MASTER_SELECT_DDR,

			{ 1, 0, 16, 20, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 } },

	[IPA_4_5][IPA_CLIENT_ETHERNET_PROD]	  = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_SRC,

			true,

			IPA_DPS_HPS_REP_SEQ_TYPE_2PKT_PROC_PASS_NO_DEC_UCP_DMAP,

			QMB_MASTER_SELECT_DDR,

			{ 12, 0, 8, 16, IPA_EE_UC, GSI_SMART_PRE_FETCH, 4 } },

	[IPA_4_5][IPA_CLIENT_Q6_WAN_PROD]         = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_SRC,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 5, 0, 16, 28, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 8 } },

	[IPA_4_5][IPA_CLIENT_Q6_CMD_PROD]	  = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_SRC,

			false,

			IPA_DPS_HPS_SEQ_TYPE_PKT_PROCESS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 6, 1, 20, 24, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 8 } },

	[IPA_4_5][IPA_CLIENT_Q6_DL_NLO_DATA_PROD] = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_SRC,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 8, 2, 27, 32, IPA_EE_Q6, GSI_FREE_PRE_FETCH, 3 } },

	/* Only for test purpose */

	[IPA_4_5][IPA_CLIENT_TEST_PROD]           = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_SRC,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 0, 11, 8, 16, IPA_EE_AP } },

	[IPA_4_5][IPA_CLIENT_TEST1_PROD]          = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_SRC,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 0, 11, 8, 16, IPA_EE_AP } },

	[IPA_4_5][IPA_CLIENT_TEST2_PROD]          = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_SRC,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 1, 0, 8, 16, IPA_EE_AP } },

	[IPA_4_5][IPA_CLIENT_TEST3_PROD]          = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_SRC,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 9, 12, 8, 16, IPA_EE_AP } },

	[IPA_4_5][IPA_CLIENT_TEST4_PROD]          = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_SRC,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 11, 14, 8, 16, IPA_EE_AP } },



	[IPA_4_5][IPA_CLIENT_WLAN1_CONS]          = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_DST,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 24, 3, 8, 14, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 } },

	[IPA_4_5][IPA_CLIENT_USB_CONS]            = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_DST,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 25, 16, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5][IPA_CLIENT_USB_DPL_CONS]        = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_DST,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 15, 15, 5, 5, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5][IPA_CLIENT_APPS_LAN_CONS]       = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_DST,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 16, 10, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5][IPA_CLIENT_APPS_WAN_CONS]       = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_DST,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 14, 1, 9, 9, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5][IPA_CLIENT_ODU_EMB_CONS]        = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_DST,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 23, 8, 9, 9, IPA_EE_AP, GSI_SMART_PRE_FETCH, 4 } },

	[IPA_4_5][IPA_CLIENT_ETHERNET_CONS]	  = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_DST,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 28, 1, 9, 9, IPA_EE_UC } },

	[IPA_4_5][IPA_CLIENT_Q6_LAN_CONS]         = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_DST,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 17, 3, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5][IPA_CLIENT_Q6_WAN_CONS]         = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_DST,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 21, 7, 9, 9, IPA_EE_Q6, GSI_ESCAPE_BUF_ONLY, 0 } },

	[IPA_4_5][IPA_CLIENT_Q6_UL_NLO_DATA_CONS] = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_DST,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 19, 5, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 } },

	[IPA_4_5][IPA_CLIENT_Q6_UL_NLO_ACK_CONS]  = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_DST,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 20, 6, 5, 5, IPA_EE_Q6, GSI_SMART_PRE_FETCH, 2 } },

	[IPA_4_5][IPA_CLIENT_Q6_QBAP_STATUS_CONS] = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_DST,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,
@@ -2209,38 +2206,38 @@ static const struct ipa_ep_configuration ipa3_ep_mapping 
	/* Only for test purpose */

	/* MBIM aggregation test pipes should have the same QMB as USB_CONS */

	[IPA_4_5][IPA_CLIENT_TEST_CONS]           = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_DST,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 14, 1, 9, 9, IPA_EE_AP } },

	[IPA_4_5][IPA_CLIENT_TEST1_CONS]          = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_DST,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 14, 1, 9, 9, IPA_EE_AP } },

	[IPA_4_5][IPA_CLIENT_TEST2_CONS]          = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_DST,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 24, 3, 8, 14, IPA_EE_AP } },

	[IPA_4_5][IPA_CLIENT_TEST3_CONS]          = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_DST,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 25, 16, 9, 9, IPA_EE_AP } },

	[IPA_4_5][IPA_CLIENT_TEST4_CONS]          = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_DST,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 27, 18, 9, 9, IPA_EE_AP } },

	/* Dummy consumer (pipe 31) is used in L2TP rt rule */

	[IPA_4_5][IPA_CLIENT_DUMMY_CONS]          = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_DST,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,
@@ -2297,7 +2294,7 @@ static const struct ipa_ep_configuration ipa3_ep_mapping 
			{ 10, 13, 8, 16, IPA_EE_AP, GSI_ESCAPE_BUF_ONLY, 0 } },

	/* Only for test purpose */

	[IPA_4_5_MHI][IPA_CLIENT_TEST_PROD]           = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_SRC,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,
@@ -2372,7 +2369,7 @@ static const struct ipa_ep_configuration ipa3_ep_mapping 


	/* Dummy consumer (pipe 31) is used in L2TP rt rule */

	[IPA_4_5_MHI][IPA_CLIENT_DUMMY_CONS]          = {

			true, IPA_v4_5_GROUP_UL_DL,

			true, IPA_v4_5_GROUP_UL_DL_DST,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,
@@ -6366,7 +6363,7 @@ static void ipa3_write_rsrc_grp_type_reg(int group_index, 
		if (src) {

			switch (group_index) {

			case IPA_v4_5_MHI_GROUP_PCIE:

			case IPA_v4_5_GROUP_UL_DL:

			case IPA_v4_5_GROUP_UL_DL_SRC:

				ipahal_write_reg_n_fields(

					IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n,

					n, val);
@@ -6390,8 +6387,8 @@ static void ipa3_write_rsrc_grp_type_reg(int group_index, 
			}

		} else {

			switch (group_index) {

			case IPA_v4_5_MHI_GROUP_PCIE:

			case IPA_v4_5_GROUP_UL_DL:

			case IPA_v4_5_GROUP_UL_DL_DST:

			case IPA_v4_5_MHI_GROUP_DDR:

				ipahal_write_reg_n_fields(

					IPA_DST_RSRC_GRP_01_RSRC_TYPE_n,

					n, val);