Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b4af3f7c authored by Magnus Damm's avatar Magnus Damm Committed by Andi Kleen
Browse files

[PATCH] i386: mark cpu init functions as __cpuinit, data as __cpuinitdata 



Mark i386-specific cpu init functions as __cpuinit. They are all
only called from arch/i386/common.c:identify_cpu() that already is marked as
__cpuinit. This patch also removes the empty function init_umc().

Signed-off-by: default avatarMagnus Damm <magnus@valinux.co.jp>
Signed-off-by: default avatarAndi Kleen <ak@suse.de>
parent 95414930

arch/i386/kernel/cpu/amd.c

+1 −1
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ 
extern void vide(void);

__asm__(".align 4\nvide: ret");



static void __init init_amd(struct cpuinfo_x86 *c)

static void __cpuinit init_amd(struct cpuinfo_x86 *c)

{

	u32 l, h;

	int mbytes = num_physpages >> (20-PAGE_SHIFT);

arch/i386/kernel/cpu/centaur.c

+10 −10
Original line number Diff line number Diff line
@@ -9,7 +9,7 @@ 


#ifdef CONFIG_X86_OOSTORE



static u32 __init power2(u32 x)

static u32 __cpuinit power2(u32 x)

{

	u32 s=1;

	while(s<=x)
@@ -22,7 +22,7 @@ static u32 __init power2(u32 x) 
 *	Set up an actual MCR

 */

 

static void __init centaur_mcr_insert(int reg, u32 base, u32 size, int key)

static void __cpuinit centaur_mcr_insert(int reg, u32 base, u32 size, int key)

{

	u32 lo, hi;
@@ -40,7 +40,7 @@ static void __init centaur_mcr_insert(int reg, u32 base, u32 size, int key) 
 *	Shortcut: We know you can't put 4Gig of RAM on a winchip

 */



static u32 __init ramtop(void)		/* 16388 */

static u32 __cpuinit ramtop(void)		/* 16388 */

{

	int i;

	u32 top = 0;
@@ -91,7 +91,7 @@ static u32 __init ramtop(void) /* 16388 */ 
 *	Compute a set of MCR's to give maximum coverage

 */



static int __init centaur_mcr_compute(int nr, int key)

static int __cpuinit centaur_mcr_compute(int nr, int key)

{

	u32 mem = ramtop();

	u32 root = power2(mem);
@@ -166,7 +166,7 @@ static int __init centaur_mcr_compute(int nr, int key) 
	return ct;

}



static void __init centaur_create_optimal_mcr(void)

static void __cpuinit centaur_create_optimal_mcr(void)

{

	int i;

	/*
@@ -189,7 +189,7 @@ static void __init centaur_create_optimal_mcr(void) 
		wrmsr(MSR_IDT_MCR0+i, 0, 0);

}



static void __init winchip2_create_optimal_mcr(void)

static void __cpuinit winchip2_create_optimal_mcr(void)

{

	u32 lo, hi;

	int i;
@@ -227,7 +227,7 @@ static void __init winchip2_create_optimal_mcr(void) 
 *	Handle the MCR key on the Winchip 2.

 */



static void __init winchip2_unprotect_mcr(void)

static void __cpuinit winchip2_unprotect_mcr(void)

{

	u32 lo, hi;

	u32 key;
@@ -239,7 +239,7 @@ static void __init winchip2_unprotect_mcr(void) 
	wrmsr(MSR_IDT_MCR_CTRL, lo, hi);

}



static void __init winchip2_protect_mcr(void)

static void __cpuinit winchip2_protect_mcr(void)

{

	u32 lo, hi;
@@ -257,7 +257,7 @@ static void __init winchip2_protect_mcr(void) 
#define RNG_ENABLED	(1 << 3)

#define RNG_ENABLE	(1 << 6)	/* MSR_VIA_RNG */



static void __init init_c3(struct cpuinfo_x86 *c)

static void __cpuinit init_c3(struct cpuinfo_x86 *c)

{

	u32  lo, hi;
@@ -303,7 +303,7 @@ static void __init init_c3(struct cpuinfo_x86 *c) 
	display_cacheinfo(c);

}



static void __init init_centaur(struct cpuinfo_x86 *c)

static void __cpuinit init_centaur(struct cpuinfo_x86 *c)

{

	enum {

		ECX8=1<<1,

arch/i386/kernel/cpu/common.c

+1 −1
Original line number Diff line number Diff line
@@ -36,7 +36,7 @@ struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {}; 


extern int disable_pse;



static void default_init(struct cpuinfo_x86 * c)

static void __cpuinit default_init(struct cpuinfo_x86 * c)

{

	/* Not much we can do here... */

	/* Check if at least it has cpuid */

arch/i386/kernel/cpu/cyrix.c

+16 −16
Original line number Diff line number Diff line
@@ -52,25 +52,25 @@ static void __init do_cyrix_devid(unsigned char *dir0, unsigned char *dir1) 
 * Actually since bugs.h doesn't even reference this perhaps someone should

 * fix the documentation ???

 */

static unsigned char Cx86_dir0_msb __initdata = 0;

static unsigned char Cx86_dir0_msb __cpuinitdata = 0;



static char Cx86_model[][9] __initdata = {

static char Cx86_model[][9] __cpuinitdata = {

	"Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ",

	"M II ", "Unknown"

};

static char Cx486_name[][5] __initdata = {

static char Cx486_name[][5] __cpuinitdata = {

	"SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx",

	"SRx2", "DRx2"

};

static char Cx486S_name[][4] __initdata = {

static char Cx486S_name[][4] __cpuinitdata = {

	"S", "S2", "Se", "S2e"

};

static char Cx486D_name[][4] __initdata = {

static char Cx486D_name[][4] __cpuinitdata = {

	"DX", "DX2", "?", "?", "?", "DX4"

};

static char Cx86_cb[] __initdata = "?.5x Core/Bus Clock";

static char cyrix_model_mult1[] __initdata = "12??43";

static char cyrix_model_mult2[] __initdata = "12233445";

static char Cx86_cb[] __cpuinitdata = "?.5x Core/Bus Clock";

static char cyrix_model_mult1[] __cpuinitdata = "12??43";

static char cyrix_model_mult2[] __cpuinitdata = "12233445";



/*

 * Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old
@@ -82,7 +82,7 @@ static char cyrix_model_mult2[] __initdata = "12233445"; 


extern void calibrate_delay(void) __init;



static void __init check_cx686_slop(struct cpuinfo_x86 *c)

static void __cpuinit check_cx686_slop(struct cpuinfo_x86 *c)

{

	unsigned long flags;
@@ -107,7 +107,7 @@ static void __init check_cx686_slop(struct cpuinfo_x86 *c) 
}





static void __init set_cx86_reorder(void)

static void __cpuinit set_cx86_reorder(void)

{

	u8 ccr3;
@@ -122,7 +122,7 @@ static void __init set_cx86_reorder(void) 
	setCx86(CX86_CCR3, ccr3);

}



static void __init set_cx86_memwb(void)

static void __cpuinit set_cx86_memwb(void)

{

	u32 cr0;
@@ -137,7 +137,7 @@ static void __init set_cx86_memwb(void) 
	setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14 );

}



static void __init set_cx86_inc(void)

static void __cpuinit set_cx86_inc(void)

{

	unsigned char ccr3;
@@ -158,7 +158,7 @@ static void __init set_cx86_inc(void) 
 *	Configure later MediaGX and/or Geode processor.

 */



static void __init geode_configure(void)

static void __cpuinit geode_configure(void)

{

	unsigned long flags;

	u8 ccr3, ccr4;
@@ -184,14 +184,14 @@ static void __init geode_configure(void) 




#ifdef CONFIG_PCI

static struct pci_device_id __initdata cyrix_55x0[] = {

static struct pci_device_id __cpuinitdata cyrix_55x0[] = {

	{ PCI_DEVICE(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510) },

	{ PCI_DEVICE(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520) },

	{ },

};

#endif



static void __init init_cyrix(struct cpuinfo_x86 *c)

static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)

{

	unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0;

	char *buf = c->x86_model_id;
@@ -346,7 +346,7 @@ static void __init init_cyrix(struct cpuinfo_x86 *c) 
/*

 * Handle National Semiconductor branded processors

 */

static void __init init_nsc(struct cpuinfo_x86 *c)

static void __cpuinit init_nsc(struct cpuinfo_x86 *c)

{

	/* There may be GX1 processors in the wild that are branded

	 * NSC and not Cyrix.

arch/i386/kernel/cpu/nexgen.c

+1 −1
Original line number Diff line number Diff line
@@ -27,7 +27,7 @@ static int __init deep_magic_nexgen_probe(void) 
	return  ret;

}



static void __init init_nexgen(struct cpuinfo_x86 * c)

static void __cpuinit init_nexgen(struct cpuinfo_x86 * c)

{

	c->x86_cache_size = 256; /* A few had 1 MB... */

}