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Commit b426f985 authored by Deepak M's avatar Deepak M Committed by Jani Nikula
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drm/i915/glk: Program new MIPI DSI PHY registers for GLK 



Program the clk lane and tlpx time count registers
to configure DSI PHY.

v2: Addressed Jani's Review comments(renamed bit field macros)
v3: Program clk lane timing reg same as dphy param reg.
v4: Removed "line over 80 character" warning

Signed-off-by: default avatarDeepak M <m.deepak@intel.com>
Signed-off-by: default avatarMadhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1487335415-14766-3-git-send-email-madhav.chauhan@intel.com
parent 39299838

drivers/gpu/drm/i915/i915_reg.h

+8 −0
Original line number Diff line number Diff line
@@ -8625,6 +8625,14 @@ enum { 
#define  LP_BYTECLK_SHIFT				0

#define  LP_BYTECLK_MASK				(0xffff << 0)



#define _MIPIA_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb0a4)

#define _MIPIC_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb8a4)

#define MIPI_TLPX_TIME_COUNT(port)	 _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)



#define _MIPIA_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb098)

#define _MIPIC_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb898)

#define MIPI_CLK_LANE_TIMING(port)	 _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)



/* bits 31:0 */

#define _MIPIA_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb064)

#define _MIPIC_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb864)

drivers/gpu/drm/i915/intel_dsi.c

+8 −0
Original line number Diff line number Diff line
@@ -1309,6 +1309,14 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder, 
		 */

		I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);



		if (IS_GEMINILAKE(dev_priv)) {

			I915_WRITE(MIPI_TLPX_TIME_COUNT(port),

					intel_dsi->lp_byte_clk);

			/* Shadow of DPHY reg */

			I915_WRITE(MIPI_CLK_LANE_TIMING(port),

					intel_dsi->dphy_reg);

		}



		/* the bw essential for transmitting 16 long packets containing

		 * 252 bytes meant for dcs write memory command is programmed in

		 * this register in terms of byte clocks. based on dsi transfer