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Commit b41953e3 authored by Chris Lew's avatar Chris Lew Committed by Gerrit - the friendly Code Review server
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ARM: dts: Add MSM QMP nodes for sdm855 



QMP is a lighweight messaging protocol to remote procs within the SoC.
Add device nodes to enable communication to AOP and NPU.

Change-Id: I03c092cbbd2a88f2a79d92a291422ce9464d4bb8
Signed-off-by: default avatarChris Lew <clew@codeaurora.org>
parent 98618248

arch/arm64/boot/dts/qcom/sdm855.dtsi

+39 −0
Original line number Diff line number Diff line
@@ -1508,6 +1508,45 @@ 
		};

	};



	qmp_aop: qcom,qmp-aop@c300000 {

		compatible = "qcom,qmp-mbox";

		reg = <0xc300000 0x1000>, <0x17c0000C 0x4>;

		reg-names = "msgram", "irq-reg-base";

		qcom,irq-mask = <0x1>;

		interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;



		label = "aop";

		priority = <0>;

		mbox-desc-offset = <0x0>;

		#mbox-cells = <1>;

	};



	qmp_npu0: qcom,qmp-npu-low@9818000 {

		compatible = "qcom,qmp-mbox";

		reg = <0x9818000 0x8000>, <0x17c00010 0x4>;

		reg-names = "msgram", "irq-reg-base";

		qcom,irq-mask = <0x20>;

		interrupts = <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;



		label = "npu_qmp_low";

		priority = <0>;

		mbox-desc-offset = <0x0>;

		#mbox-cells = <1>;

	};



	qmp_npu1: qcom,qmp-npu-high@9818200 {

		compatible = "qcom,qmp-mbox";

		reg = <0x9818000 0x8000>, <0x17c00010 0x4>;

		reg-names = "msgram", "irq-reg-base";

		qcom,irq-mask = <0x40>;

		interrupts = <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>;



		label = "npu_qmp_high";

		priority = <1>;

		mbox-desc-offset = <0x200>;

		#mbox-cells = <1>;

	};



	system_pm {

		compatible = "qcom,system-pm";

		mboxes = <&apps_rsc 0>;