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Commit b404bcfb authored by Manish Jaggi's avatar Manish Jaggi Committed by Bjorn Helgaas
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PCI: Add ACS quirk for all Cavium devices 



Cavium devices matching this quirk do not perform peer-to-peer with other
functions, allowing masking out these bits as if they were unimplemented in
the ACS capability.

Signed-off-by: default avatarManish Jaggi <mjaggi@caviumnetworks.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Acked-by: default avatarTirumalesh Chalamarla <tchalamarla@cavium.com>
parent 92e963f5

drivers/pci/quirks.c

+15 −0
Original line number Diff line number Diff line
@@ -3832,6 +3832,19 @@ static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) 
#endif

}



static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)

{

	/*

	 * Cavium devices matching this quirk do not perform peer-to-peer

	 * with other functions, allowing masking out these bits as if they

	 * were unimplemented in the ACS capability.

	 */

	acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |

		       PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);



	return acs_flags ? 0 : 1;

}



/*

 * Many Intel PCH root ports do provide ACS-like features to disable peer

 * transactions and validate bus numbers in requests, but do not provide an
@@ -3984,6 +3997,8 @@ static const struct pci_dev_acs_enabled { 
	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },

	{ 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */

	{ 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */

	/* Cavium ThunderX */

	{ PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },

	{ 0 }

};