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Commit b3d23914 authored by Lokesh Batra's avatar Lokesh Batra
Browse files

msm: kgsl: Add support for A640 GPU



Add new GPU ID and required initial settings
to support Graphics functionality on SDM855.

Change-Id: Iadeabd74c2b1f3bb4ae5bd9193d6451233c92b29
Signed-off-by: default avatarLokesh Batra <lbatra@codeaurora.org>
parent b2bdf7dc
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+7 −1
Original line number Diff line number Diff line
/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
@@ -406,6 +406,7 @@
#define A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL      0xF810

#define A6XX_RBBM_VBIF_CLIENT_QOS_CNTL   0x00010
#define A6XX_RBBM_GBIF_CLIENT_QOS_CNTL   0x00011
#define A6XX_RBBM_GPR0_CNTL              0x00018
#define A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0001f
#define A6XX_RBBM_INT_CLEAR_CMD          0x00037
@@ -521,6 +522,7 @@
#define A6XX_RBBM_CLOCK_HYST_GMU_GX      0x0011a
#define A6XX_RBBM_CLOCK_MODE_HLSQ	 0x0011b
#define A6XX_RBBM_CLOCK_DELAY_HLSQ       0x0011c
#define A6XX_RBBM_CLOCK_HYST_HLSQ        0x0011d

/* DBGC_CFG registers */
#define A6XX_DBGC_CFG_DBGBUS_SEL_A                  0x600
@@ -809,6 +811,10 @@
#define GBIF_AXI1_WRITE_DATA_TOTAL_BEATS   47

/* GBIF registers */
#define A6XX_GBIF_QSB_SIDE0               0x3c03
#define A6XX_GBIF_QSB_SIDE1               0x3c04
#define A6XX_GBIF_QSB_SIDE2               0x3c05
#define A6XX_GBIF_QSB_SIDE3               0x3c06
#define A6XX_GBIF_HALT                    0x3c45
#define A6XX_GBIF_HALT_ACK                0x3c46
#define A6XX_GBIF_HALT_MASK               0x2
+20 −1
Original line number Diff line number Diff line
/* Copyright (c) 2002,2007-2017, The Linux Foundation. All rights reserved.
/* Copyright (c) 2002,2007-2018, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
@@ -379,4 +379,23 @@ static const struct adreno_gpu_core adreno_gpulist[] = {
		.gpmu_major = 0x1,
		.gpmu_minor = 0x001,
	},
	{
		.gpurev = ADRENO_REV_A640,
		.core = 6,
		.major = 4,
		.minor = 0,
		.patchid = ANY_ID,
		.features = ADRENO_64BIT | ADRENO_RPMH,
		.sqefw_name = "a630_sqe.fw",
		.zap_name = "a640_zap",
		.gpudev = &adreno_a6xx_gpudev,
		.gmem_size = SZ_1M, //Verified 1MB
		.num_protected_regs = 0x20,
		.busy_mask = 0xFFFFFFFE,
		.gpmufw_name = "a640_gmu.bin",
		.gpmu_major = 0x0,
		.gpmu_minor = 0x005,
		.gpmu_tsens = 0x000C000D,
		.max_power = 5448,
	},
};
+4 −2
Original line number Diff line number Diff line
/* Copyright (c) 2008-2017, The Linux Foundation. All rights reserved.
/* Copyright (c) 2008-2018, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
@@ -207,6 +207,7 @@ enum adreno_gpurev {
	ADRENO_REV_A540 = 540,
	ADRENO_REV_A615 = 615,
	ADRENO_REV_A630 = 630,
	ADRENO_REV_A640 = 640,
};

#define ADRENO_START_WARM 0
@@ -1245,6 +1246,7 @@ static inline int adreno_is_a6xx(struct adreno_device *adreno_dev)

ADRENO_TARGET(a615, ADRENO_REV_A615)
ADRENO_TARGET(a630, ADRENO_REV_A630)
ADRENO_TARGET(a640, ADRENO_REV_A640)

static inline int adreno_is_a630v1(struct adreno_device *adreno_dev)
{
@@ -1871,7 +1873,7 @@ static inline void adreno_perfcntr_active_oob_put(

static inline bool adreno_has_gbif(struct adreno_device *adreno_dev)
{
	if (adreno_is_a615(adreno_dev))
	if (adreno_is_a615(adreno_dev) || adreno_is_a640(adreno_dev))
		return true;
	else
		return false;
+125 −1
Original line number Diff line number Diff line
@@ -59,9 +59,19 @@ static const struct adreno_vbif_data a615_gbif[] = {
	{0, 0},
};

static const struct adreno_vbif_data a640_gbif[] = {
	{A6XX_GBIF_QSB_SIDE0, 0x00071620},
	{A6XX_GBIF_QSB_SIDE1, 0x00071620},
	{A6XX_GBIF_QSB_SIDE2, 0x00071620},
	{A6XX_GBIF_QSB_SIDE3, 0x00071620},
	{A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3},
	{0, 0},
};

static const struct adreno_vbif_platform a6xx_vbif_platforms[] = {
	{ adreno_is_a630, a630_vbif },
	{ adreno_is_a615, a615_gbif },
	{ adreno_is_a640, a640_gbif },
};

struct kgsl_hwcg_reg {
@@ -242,6 +252,119 @@ static const struct kgsl_hwcg_reg a615_hwcg_regs[] = {
	{A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}
};

static const struct kgsl_hwcg_reg a640_hwcg_regs[] = {
	{A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
	{A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02222220},
	{A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02222220},
	{A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02222220},
	{A6XX_RBBM_CLOCK_DELAY_SP0, 0x0000F3CF},
	{A6XX_RBBM_CLOCK_DELAY_SP1, 0x0000F3CF},
	{A6XX_RBBM_CLOCK_DELAY_SP2, 0x0000F3CF},
	{A6XX_RBBM_CLOCK_DELAY_SP3, 0x0000F3CF},
	{A6XX_RBBM_CLOCK_HYST_SP0, 0x00000081},
	{A6XX_RBBM_CLOCK_HYST_SP1, 0x00000081},
	{A6XX_RBBM_CLOCK_HYST_SP2, 0x00000081},
	{A6XX_RBBM_CLOCK_HYST_SP3, 0x00000081},
	{A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
	{A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
	{A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222},
	{A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222},
	{A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
	{A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
	{A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222},
	{A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222},
	{A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777},
	{A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
	{A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
	{A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777},
	{A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777},
	{A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111},
	{A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
	{A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
	{A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111},
	{A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111},
	{A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
	{A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
	{A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
	{A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},
	{A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222},
	{A6XX_RBBM_CLOCK_CNTL2_RB1, 0x01202222},
	{A6XX_RBBM_CLOCK_CNTL2_RB2, 0x01202222},
	{A6XX_RBBM_CLOCK_CNTL2_RB3, 0x01202222},
	{A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
	{A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
	{A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
	{A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
	{A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
	{A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00},
	{A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00},
	{A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00},
	{A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022},
	{A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
	{A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
	{A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
	{A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
	{A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
	{A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222},
	{A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
	{A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
	{A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
	{A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
	{A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
	{A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
	{A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
	{A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
	{A6XX_RBBM_CLOCK_CNTL, 0xAAA8AA82},
	{A6XX_RBBM_ISDB_CNT, 0x00000182},
	{A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
	{A6XX_RBBM_SP_HYST_CNT, 0x00000000},
	{A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
	{A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
	{A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
};

static const struct {
	int (*devfunc)(struct adreno_device *adreno_dev);
	const struct kgsl_hwcg_reg *regs;
@@ -249,6 +372,7 @@ static const struct {
} a6xx_hwcg_registers[] = {
	{adreno_is_a630, a630_hwcg_regs, ARRAY_SIZE(a630_hwcg_regs)},
	{adreno_is_a615, a615_hwcg_regs, ARRAY_SIZE(a615_hwcg_regs)},
	{adreno_is_a640, a640_hwcg_regs, ARRAY_SIZE(a640_hwcg_regs)},
};

static struct a6xx_protected_regs {