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Commit b37245fb authored by Mao Jinlong's avatar Mao Jinlong
Browse files

ARM: dts: msm: Add missing ctis for SM6150 



Add missing ctis:

coresight-cti-dlct_cti0
coresight-cti-dlct_cti1
coresight-cti-ddr_dl_0_cti0
coresight-cti-ddr_dl_0_cti1
coresight-cti-ddr_dl_1_cti0
coresight-cti-ddr_dl_1_cti1

Change-Id: Iced2b0a8e33850fd5cf4c1459ad3fb548ee4bde4
Signed-off-by: default avatarMao Jinlong <jinlmao@codeaurora.org>
parent 34e53ec4

arch/arm64/boot/dts/qcom/sm6150-coresight.dtsi

+72 −0
Original line number Diff line number Diff line
@@ -1356,6 +1356,78 @@ 
		};

	};



	cti0_dlct: cti@6c29000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6c29000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-dlct_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";

	};



	cti1_dlct: cti@6c2a000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6c2a000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-dlct_cti1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";

	};



	cti0_ddr0: cti@6a02000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6a02000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-ddr_dl_0_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";

	};



	cti1_ddr0: cti@6a03000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6a03000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-ddr_dl_0_cti1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";

	};



	cti0_ddr1: cti@6a10000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6a10000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-ddr_dl_1_cti0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";

	};



	cti1_ddr1: cti@6a11000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6a11000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-ddr_dl_1_cti1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";

	};



	cti_mss_q6: cti@683b000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;